IS43/46R16800E, IS43/46R32400E
4Mx32, 8Mx16
128Mb DDR SDRAM
FEATURES
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VDD and VDDQ: 2.5V ± 0.2V (-5,-6)
VDD and VDDQ: 2.5V ± 0.1V (-4)
SSTL_2 compatible I/O
Double-data rate architecture; two data transfers
per clock cycle
Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
Burst Length: 2, 4 and 8
Burst Type: Sequential and Interleave mode
Programmable CAS latency: 2, 2.5, 3, and 4
Auto Refresh and Self Refresh Modes
Auto Precharge
T
ras
Lockout supported (t
rap
= t
rcd
)
JANUARY 2014
DEVICE OVERVIEW
ISSI’s 128-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit and 32-bit data word size Input
data is registered on the I/O pins on both edges of
Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
ADDRESS TABLE
Parameter
Configuration
Bank Address
Pins
Autoprecharge
Pins
Row Address
Column
Address
Refresh Count
Com./Ind./A1
A2
4M x 32
1M x 32 x 4
banks
BA0, BA1
A8/AP
4K(A0 – A11)
256(A0 – A7)
8M x 16
2M x 16 x 4
banks
BA0, BA1
A10/AP
4K(A0 – A11)
512(A0 – A8)
OPTIONS
• Configuration(s): 4Mx32, 8Mx16
• Package(s):
144 Ball BGA (x32)
66-pin TSOP-II (x16) and 60 Ball BGA (x16)
• Lead-free package available
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
4K / 64ms
4K / 16ms
4K / 64ms
4K / 16ms
KEY TIMING PARAMETERS
Speed Grade
F
ck
Max CL = 4
F
ck
Max CL = 3
F
ck
Max CL = 2.5
F
ck
Max CL = 2
-4
250
200
—
—
-5
—
200
167
133
-6
—
167
167
133
Units
MHz
MHz
MHz
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. C
1/16/14
1
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