NXP Semiconductors
Data Sheet: Technical Data
Document Number MC56F823XX
Rev. 3.0, 09/2016
Supports MC56F82323VFM,
MC56F82316VLF, MC56F82313VLC
Features
• This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. On a single chip,
each device combines the processing power of a DSP
and the functionality of an MCU, with a flexible set of
peripherals to support many target applications:
– Industrial control
– Home appliances
– Smart sensors
– Wireless charging
– Power distribution systems
– Motor control (ACIM, BLDC, PMSM, SR, stepper)
– Photovoltaic systems
– Circuit breaker
– Medical device/equipment
– Instrumentation
• DSC based on 32-bit 56800EX core
– Up to 50 MIPS at 50 MHz core frequency
– DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– Up to 32 KB flash memory
– Up to 6 KB data/program RAM
– On-chip flash memory and RAM can be mapped
into both program and data memory spaces
• Analog
– Two high-speed, 5-channel, 12-bit ADCs with
dynamic x1, x2, and x4 programmable amplifier
– Three analog comparators with integrated 6-bit DAC
references
– Up to two 12-bit digital-to-analog converters (DAC)
• One FlexPWM module with up to 6 PWM outputs
• Communication interfaces
– Up to two high-speed queued SCI (QSCI) modules
with LIN slave functionality
– One queued SPI (QSPI) module
– One I2C/SMBus port
• Timers
– One 16-bit quad timer (1 x 4 16-bit timer)
– Two Periodic Interval Timers (PITs)
• Security and integrity
– Cyclic Redundancy Check (CRC) generator
– Windowed Computer operating properly (COP)
watchdog
– External Watchdog Monitor (EWM)
• Clocks
– Two on-chip relaxation oscillators: 8 MHz (400 kHz
at standby mode) and 200 kHz
– Crystal / resonator oscillator
• System
– DMA controller
– Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
– Inter-module crossbar connection
– JTAG/enhanced on-chip emulation (EOnCE) for
unobtrusive, real-time debugging
• Operating characteristics
– Single supply: 3.0 V to 3.6 V
– 5 V–tolerant I/O (except for RESETB pin which is a
3.3 V pin only)
– Operation ambient temperature: -40°C to 105°C
• 48-pin LQFP, 32-pin LQFP and 32-pin QFN packages
MC56F823xx
MC56F823XX
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
Overview............................................................................................ 3
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
MC56F823xx Product Family.................................................3
56800EX 32-bit Digital Signal Controller (DSC) core...........3
Operation Parameters.............................................................. 4
On-Chip Memory and Memory Protection............................. 5
Interrupt Controller................................................................. 5
Peripheral highlights............................................................... 6
Block diagrams........................................................................11
7
6.1
6.2
6.3
6.4
Thermal handling ratings........................................................ 27
Moisture handling ratings........................................................27
ESD handling ratings.............................................................. 27
Voltage and current operating ratings..................................... 28
General............................................................................................... 29
7.1
7.2
7.3
7.4
7.5
General characteristics............................................................ 29
AC electrical characteristics....................................................30
Nonswitching electrical specifications....................................31
Switching specifications..........................................................36
Thermal specifications............................................................ 37
MC56F823xx signal and pin descriptions..........................................14
2.1
Signal groups...........................................................................20
8
3
Ordering parts.....................................................................................21
3.1
Determining valid orderable parts...........................................21
Peripheral operating requirements and behaviors.............................. 39
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Core modules...........................................................................39
System modules.......................................................................40
Clock modules.........................................................................40
Memories and memory interfaces........................................... 43
Analog..................................................................................... 45
Timer....................................................................................... 51
Communication interfaces.......................................................52
4
Part identification............................................................................... 21
4.1
4.2
4.3
4.4
Description.............................................................................. 21
Format..................................................................................... 21
Fields....................................................................................... 22
Example...................................................................................22
5
Terminology and guidelines...............................................................22
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Definition: Operating requirement.......................................... 22
Definition: Operating behavior............................................... 23
Definition: Attribute................................................................23
Definition: Rating....................................................................23
Result of exceeding a rating.................................................... 24
Relationship between ratings and operating requirements......24
Guidelines for ratings and operating requirements................. 25
Definition: Typical value........................................................ 25
Typical value conditions......................................................... 26
9
Design Considerations....................................................................... 57
9.1
9.2
9.3
Thermal design considerations................................................57
Electrical design considerations.............................................. 59
Power-on Reset design considerations....................................60
10 Obtaining package dimensions.......................................................... 63
11 Pinout................................................................................................. 63
11.1 Signal Multiplexing and Pin Assignments.............................. 63
11.2 Pinout diagrams.......................................................................65
12 Product documentation.......................................................................66
13 Revision History.................................................................................67
6
Ratings................................................................................................27
MC56F823xx, Rev. 3.0, 09/2016
2
NXP Semiconductors
Overview
1 Overview
1.1 MC56F823xx Product Family
The following table is the comparsion of features among members of the family.
Table 1. MC56F823xx Family
Part Number
323VFM
Core frequency (MHz)
Flash memory (KB)
RAM (KB)
Interrupt Controller
Windowed Computer
Operating Properly (WCOP)
External Watchdog Monitor
(EWM)
Periodic Interrupt Timer (PIT)
Cyclic Redundancy Check
(CRC)
Quad Timer (TMR)
12-bit Cyclic ADC channels
PWM module :
Standard channel with input
capture
1
12-bit DAC
DMA
Analog Comparators (CMP)
QSCI
QSPI
I2C/SMBus
GPIO
Package pin count
0
Yes
2
1
1
1
26
32 QFN
2
Yes
4
2
1
1
39
48 LQFP
0
Yes
2
1
1
1
26
32 LQFP
50
32
6
Yes
1
1
2
1
1x4
2x3
6
MC56F82
316V LF
50
16
4
Yes
1
1
2
1
1x4
2x5
6
313V LC
50
16
4
Yes
1
1
2
1
1x4
2x3
6
1. Input capture shares the pin with cooresponding PWM channels.
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
MC56F823xx, Rev. 3.0, 09/2016
NXP Semiconductors
3
Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
As many as 50 million instructions per second (MIPS) at 50 MHz core frequency
162 basic instructions
Instruction set supports both fractional arithmetic and integer arithmetic
32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
32-bit arithmetic and logic multi-bit shifter
Four 36-bit accumulators, including extension bits
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions enable compact code
Enhanced bit manipulation instruction set
Efficient C compiler and local variable support
Software subroutine and interrupt stack, with the stack's depth limited only by
memory
Priority level setting for interrupt levels
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation Parameters
• Up to 50 MHz operation
• Operation ambient temperature:
-40
o
C to 105
o
C
• Single 3.3 V power supply
• Supply range: V
DD
- V
SS
= 2.7 V to 3.6 V, V
DDA
- V
SSA
= 2.7 V to 3.6 V
MC56F823xx, Rev. 3.0, 09/2016
4
NXP Semiconductors
Overview
1.4 On-Chip Memory and Memory Protection
• Dual Harvard architecture permits as many as three simultaneous accesses to
program and data memory
• Internal flash memory with security and protection to prevent unauthorized access
• Memory resource protection (MRP) unit to protect supervisor programs and
resources from user programs
• Programming code can reside in flash memory during flash programming
• The dual-port RAM controller supports concurrent instruction fetches and data
accesses, or dual data accesses by the core.
• Concurrent accesses provide increased performance.
• The data and instruction arrive at the core in the same cycle, reducing latency.
• On-chip memory
• Up to 32 KB program/data flash memory
• Up to 4 KB dual port data/program RAM
1.5 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
MC56F823xx, Rev. 3.0, 09/2016
NXP Semiconductors
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