EEWORLDEEWORLDEEWORLD

Part Number

Search

9LRS3165BGILFT

Description
Clock Synthesizer / Jitter Cleaner 64-pin CK505 Clock Regulator Series Res
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size310KB,28 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric Compare View All

9LRS3165BGILFT Online Shopping

Suppliers Part Number Price MOQ In stock  
9LRS3165BGILFT - - View Buy Now

9LRS3165BGILFT Overview

Clock Synthesizer / Jitter Cleaner 64-pin CK505 Clock Regulator Series Res

9LRS3165BGILFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP64,.32,20
Contacts64
Manufacturer packaging codePAG64
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionTSSOP 6.1 MM 0.5MM PITCH
JESD-30 codeR-PDSO-G64
JESD-609 codee3
length17 mm
Humidity sensitivity level1
Number of terminals64
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency400 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP64,.32,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency14.318 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate125 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width6.1 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC
DATASHEET
64-pin CK505 Compatible Clock w/Fully Integrated Voltage
Regulator + Integrated Series Resistor
Recommended Application:
CK505 compatible clock with fully integrated voltage regulator and
Internal series resistor on differential outputs
Output Features:
2 - CPU differential low power push-pull pairs
9 - SRC differential low power push-pull pairs
1 - CPU/SRC selectable differential low power push-pull pair
1 - SRC/DOT selectable differential low power push-pull pair
5 - PCI, 33MHz
1 - PCI_F, 33MHz free running
1 - USB, 48MHz
1 - REF, 14.318MHz
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
Does not require external pass transistor for voltage regulator
Integrated 33ohm series resistors on differential outputs,
Z
o
=50Ω
• Supports spread spectrum modulation, default is 0.5% down
spread
Uses external 14.318MHz crystal, external crystal load caps
are required for frequency tuning
Selectable between one SRC differential push-pull pair and
two single-ended outputs
Meets PCIEX Gen2 specification on dedicated SRC outputs.
Muxed SRC outputs meet PCIEX Gen1 specification, except
SRC1.
Single-ended programmable slew rate control for RFI
reduction
Meets PCIEX <85ps cycle-to-cycle jitter for SRC[11:1]
Table 1: CPU Frequency Select Table
9LRS3165B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT_LR0
CPUC_LR0
GNDCPU
CPUT_F_LR1
CPUC_F_LR1
VDDCPU_IO
NC
CPUT_ITP_LR2/SRCT8
CPUC_ITP_LR2/SRCC8
VDDSRCI/O
SRCT_LR7/CR#_F
SRCC_LR7/CR#_E
GNDSRC
SRCT_LR6
SRCC_LR6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRCI/O
SRCC_LR10
SRCT_LR10
SRCT_LR11/CR#_H
Pin Configuration
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SEL
PCI5_F/ITP_EN
GNDPCI
VDD48
USB48M/FSLA
GND48
VDDI/O96MHz
DOT96T/SRCT_LR0
DOT96C/SRCC_LR0
GND
VDD
27FIX/LCDT/SRCT_LR1/SE1
27SS/LCDC/SRCC_LR1/SE2
GND
VDDPLL3I/O
SRCT_LR2/SATACLKT
SRCC_LR2/SATACLKC
GNDSRC
SRCT_LR3/CR#_C
SRCC_LR3/CR#_D
VDDSRCI/O
SRCT_LR4
SRCC_LR4
GNDSRC
SRCT_LR9
SRCC_LR9
SRCC_LR11/CR#_G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64-TSSOP
2
1
1
CPU
SRC
PCI
REF
USB
DOT
FS
L
C
FS
L
B
FS
L
A
MHz
MHz
MHz
MHz
MHz
MHz
B0b7
B0b6
B0b5
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66
48.00
100.00
33.33 14.318
96.00
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
ICS9LRS3165B
1533B—01/06/15
1

9LRS3165BGILFT Related Products

9LRS3165BGILFT 9LRS3165BGLF 9LRS3165BKLFT 9LRS3165BGILF 9LRS3165BKILF 9LRS3165BKLF
Description Clock Synthesizer / Jitter Cleaner 64-pin CK505 Clock Regulator Series Res Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK Clock Synthesizer / Jitter Cleaner 64-pin CK505 Clock Regulator Series Res Clock Synthesizer / Jitter Cleaner 64-pin CK505 Clock Regulator Series Res Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
LED lighting color is as important as light efficiency
Introduction: In terms of the quality of light source, high luminous efficiency and high color rendering index are the key to LED . Zhang Haicong, chairman of the Shanghai Illuminating Society, believ...
LED123 LED Zone
The Analog Engineer's Circuit Design Cookbook: Amplifiers
Awesome free downloadable resource here! Having an amplifier design challenge? Don’t worry!Whether you are faced with the challenge of solving an ambient temperature monitoring problem, a low-side cur...
qwqwqw2088 Analogue and Mixed Signal
The 6th WiCOM2010 Call for Papers (Ei&ISTP Indexed)
The 6th International Conference onWireless Communications, Networking and Mobile Computing (WiCOM2010)CALL FOR PAPERS[url=http://www.wicom-meeting.org/2010/]http://www.wicom-meeting.org/2010/[/url]Ch...
pz41081422 DSP and ARM Processors
Does anyone have a program for repeated acquisition of AD12 sequence?
When the sequence is repeatedly collected, do we need to determine the interrupt bit of the last channel?After the data in AD12MEM is read,it will automatically collect again....
litiantao Microcontroller MCU
MSP430 IAP program interrupt vector redirection
In the IAP upgrade program of MSP430, interrupts are redirected in the boot program code. Why do we need to use vector mapping? Do the interrupts of the boot program and the application program confli...
马建鲁 Microcontroller MCU
When compiling PB, it says that boot may not be supported. What should I do? ? ?
PB Debugger Warning:Debugger service map is set to none.If your image has debugging support it may not boot properly. PB Debugger Cannot initialize the Kernel Debugger. PB Debugger Debugger could not ...
yyyjjj Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 384  74  817  1300  758  8  2  17  27  16 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号