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KMPC8347ZQAGDB

Description
Microprocessors - MPU 8347 PBGA PB W/O ENC
Categorysemiconductor    The embedded processor and controller   
File Size567KB,99 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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KMPC8347ZQAGDB Overview

Microprocessors - MPU 8347 PBGA PB W/O ENC

KMPC8347ZQAGDB Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerNXP
Product CategoryMicroprocessors - MPU
RoHSN
Mounting StyleSMD/SMT
Package / CasePBGA-620
Coree300
Number of Cores1 Core
Data Bus Width32 bit
Maximum Clock Frequency400 MHz
L1 Cache Instruction Memory32 kB
L1 Cache Data Memory32 kB
Operating Supply Voltage1.2 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 105 C
PackagingTray
Memory TypeL1 Cache
Interface TypeEthernet, I2C, PCIe, SPI, UART, USB
Number of I/Os52 I/O
I/O Voltage1.8 V, 2.5 V, 3.3 V
Instruction TypeFloating Point
Moisture SensitiveYes
Number of Timers/Counters8 x 32 bit
Processor SeriesPowerQUICC II Pro
Factory Pack Quantity2
Watchdog TimersWatchdog Timer
Unit Weight0.153759 oz
Freescale Semiconductor
Technical Data
Document Number: MPC8347EAEC
Rev. 12, 09/2011
MPC8347EA PowerQUICC II Pro
Integrated Host Processor Hardware
Specifications
The MPC8347EA PowerQUICC II Pro is a next generation
PowerQUICC II integrated host processor. The
MPC8347EA contains a processor core built on Power
Architecture® technology with system logic for networking,
storage, and general-purpose embedded applications. For
functional characteristics of the processor, refer to the
MPC8349EA PowerQUICC II Pro Integrated Host
Processor Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC8347EA product summary page on our website,
as listed on the back cover of this document, or contact your
local Freescale sales office.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 16
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ethernet: Three-Speed Ethernet, MII Management . 23
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
System Design Information . . . . . . . . . . . . . . . . . . . 91
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 94
Document Revision History . . . . . . . . . . . . . . . . . . . 96
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© 2006–2011 Freescale Semiconductor, Inc. All rights reserved.
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