NCP81109C
Single-Phase Voltage
Regulator with SVID
Interface for Computing
Applications
High Switching Frequency, High
Efficiency, Integrated Power MOSFETs
The NCP81109C, a single−phase synchronous buck regulator,
integrates power MOSFETs to provide a high−efficiency and
compact−footprint power management solution for new generation
computing CPUs. The device is able to deliver up to 14 A TDC output
current on an adjustable output with SVID interface. Operating in high
switching frequency up to 1.2 MHz allows employing small size
inductors and capacitors while maintaining high efficiency due to
integrated solution with high performance power MOSFETs.
Current−mode RPM control with feedforward from both input power
supply and output voltage ensures stable operation over wide
operation condition. The NCP81109C is in a QFN48 6 x 6 mm
package.
Features
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MARKING
DIAGRAM
1
1 48
QFN48
CASE 485CJ
NCP81109C
AWLYYWWG
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NCP81109C= Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
Meets Intel® Server Specifications
5 V to 20 V Input Voltage Range
0.9 V/1.35 V Fixed Boot Voltage
Adjustable Output Voltage with SVID Interface
Integrated Gate Driver and Power MOSFETs
Up to 14 A TDC Output Current
500 kHz ~ 1.2 MHz Switching Frequency
Current−Mode RPM Control
Programmable SVID Address and ICCMax
Programmable DVID Feed−Forward to Support Fast DVID
Feedforward Operation for Input Supply Voltage and Output Voltage
Output Over−Voltage and Under−Voltage Protections
External Current Limitation Programming with Inductor Current
Sense
•
QFN48, 6 x 6 mm, 0.4 mm Pitch Package
•
This is a Pb−Free Device
Typical Applications
ORDERING INFORMATION
Device
NCP81109CMNTXG
Package
QFN48
(Pb−Free)
Shipping
†
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
•
Server Applications
©
Semiconductor Components Industries, LLC, 2014
May, 2014
−
Rev. 0
1
Publication Order Number:
NCP81109C/D
NCP81109C
48
EN
47
VCC
46
VSP
45
VSN
44
DIFFOUT
43
FB
42
COMP
41
FREQ
40
CSREF
39
CSSUM
38
CSCOMP
37
ILIM
IOUT 36
IMAX 35
GND
49
TSENSE 34
VCCP 33
GND 32
VBOOT 31
GL 30
SW 29
VIN
50
SW
51
SW 28
SW 27
SW 26
SW 25
PGND
PGND
PGND
PGND
PGND
23
PGND
24
VIN
VIN
VIN
VIN
VIN
17
SW
18
1
2
3
4
5
6
7
8
9
VRHOT#
SDIO
ALERT#
SCLK
GND
VRRDY
VIN
BST
GH
10 SW
11 VIN
12 VIN
13
14
15
16
19
20
21
22
Figure 1. Pin Configuration
(Top View)
VIN
VIN
PGND
BST
GH
SW
SW
GL
VOUT
+5V
VCCP
VCC
GND
EN
VRHOT#
SDIO
ALERT#
SCLK
VRRDY
TSENSE
NCP81109C
ILIM
CSCOMP
CSSUM
CSREF
VBOOT
COMP
FB
DIFFOUT
IMAX
FREQ
IOUT
VSP
VSN
Figure 2.
Typical Application Circuit
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2
NCP81109C
VCCP
BST
GH
VIN
VIN
VCC
UVLO
EN
SW
Gate Drive
VCCP
GND
PGND
DAC
VRRD
Y
Control Logic
&
Protections
&
VR Ready
VSP−VSN
OCP
PWM
IMON
GL
IOUT
OCP
VRH
OT#
Current Measurement
and Limit
ILIM
Thermal
Management
TSEN
SE
PWM
Control
TSENSE
V
CS
CSREF
CSR
EF
CSS
UM
FREQ
VBO
OT
Frequency
&
VBOOT
Detection
VIN
DAC
CSCOMP
CSC
OMP
VSP−VSN
VBOOT
COMP
Current
Sense
COMP
Error
Amp
IOUT
IMAX
MUX
ADC
IMAX
TSENSE
Vref
FB
1.3V
DIFF
OUT
SDIO
SCLK
SVID Interface
Registers
Differential
Amplifier
VSP
ALE
RT#
Vref
DAC
VSN
DAC
DAC
DVID
FeedForward
Figure 3.
Functional Block Diagram
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NCP81109C
PIN DESCRIPTION
Pin
1
2
3
4
5, 32,
49
6
7,
11−17,
50
8
Name
VRHOT#
SDIO
ALERT#
SCLK
GND
VRRDY
VIN
Type
Logic Output
Logic Bidirectional
Logic Output
Logic Input
Analog Ground
Logic Output
Power Input
Description
VR HOT.
Logic low output represents over temperature.
Serial Data IO Port.
Data port of SVID interface.
ALERT.
Open−drain output. Provides a logic low valid alert signal of SVID interface.
Serial Clock.
Clock input of SVID interface.
Analog Ground.
Ground of internal control circuits. Must be connected to the system
ground.
Voltage Regulator Ready.
Open−drain output. Provides a logic high valid power good
output signal, indicating the regulator’s output is in regulation window.
Power Supply Input.
These pins are the power supply input pins of the device, which are
connected to drain of internal high−side power MOSFET. 22
mF
or more ceramic
capacitors must bypass this input to power ground. The capacitors should be placed as
close as possible to these pins.
Bootstrap.
Provides bootstrap voltage for the high−side gate driver. A 0.1
mF
~ 1
mF
ceramic capacitor is required from this pin to SW (pin 10). A 1
−
2
W
resistor may be
employed in series with the BST cap to reduce switching noise and ringing when needed.
Gate of High−Side MOSFET.
Directly connected with the gate of the high−side power
MOSFET.
Switching Node.
Provides a return path for integrated high−side gate driver. It is internally
connected to source of high−side MOSFET.
Switch Node.
Pins to be connected to an external inductor. These pins are
interconnection between internal high−side MOSFET and low−side MOSFET.
Power Ground.
These pins are the power supply ground pins of the device, which are
connected to source of internal low−side power MOSFET. Must be connected to the
system ground.
Gate of Low−Side MOSFET.
Directly connected with the gate of the low−side power
MOSFET.
Boot−Up Voltage.
A resistor from this pin to ground programs SVID address.
Voltage Supply of Gate Driver.
Power supply input pin of internal gate driver. A 4.7
mF
or
larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as
close as possible to this pin.
Temperature Sense.
An external temperature sense network is connected to this pin.
Current Maximum.
A resistor from this pin to ground programs IMAX.
OUT Current Monitor.
Provides output signal representing output current by connecting a
resistor from this pin to ground. Shorting this pin to ground disables IMON function.
Limit of Current.
A resistor from this pin to CSCOMP programs over−current threshold
with inductor current sense.
Current Sense COMP.
Output pin of current sense amplifier.
Current Sense SUM.
Inverting input of current sense amplifier.
Current Sense Reference.
Non−Inverting input of current sense amplifier.
Frequency.
A resistor from this pin to ground programs switching frequency.
Compensation.
Output pin of error amplifier.
Feedback.
Inverting input to error amplifier.
Differential Amplifier Output.
Output pin of differential voltage sense amplifier.
Voltage Sense Negative Input.
Inverting input of differential voltage sense amplifier. It is
also used for DVID feed forward function with an external resistor.
Voltage Sense Positive Input.
Non−inverting input of differential voltage sense amplifier.
BST
Power
Bidirectional
Analog Output
Power Return
Power Output
9
10
18,
25−29,
51
19−24
GH
SW
SW
PGND
Power Ground
30
31
33
GL
VBOOT
VCCP
Analog Output
Analog Input
Analog Power
34
35
36
37
38
39
40
41
42
43
44
45
46
TSENSE
IMAX
IOUT
ILIM
CSCOMP
CSSUM
CSREF
FREQ
COMP
FB
DIFFOUT
VSN
VSP
Analog
Analog Input
Analog Output
Analog Output
Analog Output
Analog Input
Analog Input
Analog Input
Analog
Analog Input
Analog Output
Analog Input
Analog Input
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4
NCP81109C
PIN DESCRIPTION
Pin
47
Name
VCC
Type
Analog Power
Description
Voltage Supply of Controller.
Power supply input pin of control circuits. A 1
mF
or larger
ceramic capacitor bypasses this input to ground. This capacitor should be placed as close
as possible to this pin.
Enable.
Logic high enables the device and logic low makes the device in standby mode.
48
EN
Logic Input
MAXIMUM RATINGS
Value
Rating
Power Supply Voltage to PGND
Switch Node to PGND
Analog Supply Voltage to GND
BST to PGND
BST to SW
GH to SW
GL to GND
VSN to GND
IOUT
PGND to GND
Other Pins
Latch up Current: (Note 1)
All pins, except digital pins
Digital pins
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Thermal Resistance Junction to Board (Note 2)
Thermal Resistance Junction to Ambient (Note 2)
Power Dissipation at T
A
= 25°C (Note 3)
Moisture Sensitivity Level (Note 4)
I
LU
Symbol
V
VIN
V
SW
V
CC,
V
CCP
BST_PGND
BST_SW
GH
GL
VSN
IOUT
PGND
−0.3
−0.3
−0.3
−0.3
−2
(<200 ns)
−0.3
−2
(<200 ns)
−0.3
−0.3
−0.3
−0.3
−100
−10
−10
−10
−40
8.2
21.8
4.59
3
Min
Max
30
30
6.5
33
38 (<50 ns)
6.5
BST+0.3
VCCP+0.3
0.3
2.5
0.3
VCC+0.3
100
10
125
100
150
Unit
V
V
V
V
V
V
V
V
V
V
V
mA
T
J
T
A
T
STG
R
θJB
R
θJA
P
D
MSL
°C
°C
°C
°C/W
°C/W
W
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latch up Current per JEDEC standard: JESD78 class II.
2. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and
2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors etc.)
3. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on T
JMAX
= 125°C and R
θJA
= 21.8°C/W.
4. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J−STD−020D.1.
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