Datasheet
Termination Regulators for DDR-SDRAMs
BD3538F
BD3538HFN
Key Specifications
Termination Input Voltage Range:
1.0V to 5.5V
VCC Input Voltage Range:
2.7V to 5.5V
VDDQ Reference Voltage Range:
1.0V to 2.75V
Output Voltage:
1/2 x V
VDDQ
V(Typ)
Output Current:
1.0A (Max)
High side FET O-Resistance:
0.4Ω(Typ)
Low side FET ON-Resistance:
0.4Ω(Typ)
Standby Current:
0.5mA (Typ)
Operating Temperature Range:
-40°C to +105°C
General Description
BD3538F/HFN is a termination regulator that complies
with JEDEC requirements for DDR-SDRAM. This
linear power supply uses a built-in N-channel MOSFET
and high-speed OP-AMPS specially designed to
provide excellent transient response. It has a
sink/source current capability of up to 1A and has a
power supply bias requirements of 3.3V to 5.0V for
driving the N-channel MOSFET. By employing an
independent reference voltage input (VDDQ) and a
feedback pin (VTTS), this termination regulator
provides excellent output voltage accuracy and load
regulation as required by JEDEC standards.
Additionally, BD3538 has a reference power supply
output (VREF) for DDR-SDRAM or a memory
controller. Unlike the VTT output that goes to “Hi-Z”
state, the VREF output is kept unchanged when EN
input is changed to “Low”, making this IC suitable for
DDR-SDRAM under “Self Refresh” state.
Packages
W(Typ) x D(Typ) x H(Max)
Features
Incorporates a push-pull power supply for
termination (VTT)
Incorporates a reference voltage circuit (VREF)
Incorporates an enabler
Incorporates an undervoltage lockout (UVLO)
Incorporates a thermal shutdown protector (TSD)
Compatible with Dual Channel (DDR-II)
SOP8
5.00mm x 6.20mm x 1.71mm
Applications
Power supply for DDR I / II - SDRAM
HSON8
2.90mm x 3.00mm x 0.60mm
Typical Application Circuit, Block Diagram
VCC
VDDQ
VTT_IN
VCC
6
5
VDDQ
7
VTT_IN
VCC
UVLO
VCC
VCC
Reference
Block
UVLO
SOFT
TSD
EN
UVLO
TSD
VCC EN
UVLO
TSD
EN
UVLO
3
VTT
8
VTT
Thermal
Protection
Enable
EN
2
TSD
VTTS
4
½x
VDDQ
EN
VREF
1
GND
○Product
structure：Silicon monolithic integrated circuit
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BD3538F
BD3538HFN
Pin Descriptions
TOP VIEW
Pin No.
1
Pin Name
GND
EN
VTTS
VREF
VDDQ
VCC
VTT_IN
VTT
FIN
(Note 1)
GND pin
Enable input pin
Detector pin for termination voltage
Reference voltage output pin
Reference voltage input pin
VCC pin
Termination input pin
Termination output pin
Substraight
(Conntct to GND)
Pin Function
Pin Configuration
GND 1
EN 2
VTTS 3
VREF 4
8 VTT
7 VTT_IN
6 VCC
5 VDDQ
2
3
4
5
6
7
8
Bottom
(Note 1) Only BD3538HFN
Description of Blocks
1.
VCC
The VCC pin is for the independent power supply input that operates the internal circuit of the IC. It is the voltage at
this pin that drives the IC’s amplifier circuits. The VCC input ranges from 3.3V to 5.5V and maximum current
consumption is 4mA. A bypass capacitor of 1 µF or so should be connected to this pin when using the IC in an
application circuit.
VDDQ
This is the power supply input pin for an internal voltage divider network. The voltage at VDDQ is halved by two 50 kΩ
internal voltage-divider resistors and the resulting voltage serves as reference for the VTT output. Since VTT =
1/2VDDQ, the JEDEC requirement for DDR-SDRAM can be satisfied by supplying the correct voltage to VDDQ. Noise
input should be avoided at the VDDQ pin as it is also included by the voltage-divider at the output. An RC filter
consisting of a resistor and a capacitor (220 Ω and 2.2 µF, for instance) may be used to reduce the noise input but
make sure that it will not significantly effect the voltage-divider’s output.
VTT_IN
VTT_IN is a power supply input pin for VTT output. Voltage in the range between 1.0V to 5.5V, but consideration must
be given to the current limit dictated by the ON-Resistance of the IC and to the change in allowable loss due to
input/output voltage difference.
Generally, the following voltages are supplied:
・
DDR I
V
VTT_IN
=2.5V
・
DDRII
V
VTT_IN
=1.8V
Take note that a high impedance voltage input at VTT_IN may result in oscillation or degradation in ripple rejection, so
connecting 10µF capacitor with minimal change in capacitance to VTT_IN terminal is recommended. However, this
impedance may depend on the characteristics of the power supply input and the impedance of the PC board wiring,
which must be carefully checked before use.
VREF
BD3538 provides a constant voltage, VREF, which is independent from the VTT output and can serve as a reference
input for memory controllers and DRAMs. The voltage level of VREF is kept constant even if the EN pin is at “Low”
level, making the use of this IC compatible with “Self Refresh” state of DRAM.
In order to stabilize the output voltage, connecting the correct combination of capacitor and resistor to VREF is
necessary. For this purpose, a combination of 1.0µF to 2.2µF ceramic capacitor, characterized by minimal variation in
capacitance and a 0.5Ω to 2.2Ω phase compensating resistor is recommended. The maximum current capability of the
VREF pin is 20mA but for an application which consumes a small amount of VREF current, using a capacitance of 1 µF
or less will do.
VTTS
VTTS is a sense pin for the load regulation of the VTT output voltage. In case the wire connecting VTT pin and the load
is too long, connecting VTTS pin to the part of the wire nearer to the load may improve load regulation.
VTT
This is the output for the DDR memory termination voltage and it has a sink/source current capability of ±1.0A. VTT
voltage tracks the voltage at VDDQ pin divided in half. The output is turned to OFF when EN pin is “Low” or when
either the VCC UVLO or the thermal shutdown protection function is activated.
Always connect a capacitor to VTT pin for loop gain and phase compensation and for reduction in output voltage
variation in the event of sudden load change. Be careful in choosing the capacitor as sufficient capacitance may cause
oscillation and high ESR (Equivalent Series Resistance) may result in increase d output voltage variation during a
sudden change in load. A 220µF or so ceramic capacitor is recommended, though ambient temperature and other
conditions should also be considered.
2.
3.
4.
5.
6.
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BD3538F
BD3538HFN
Description of Blocks - continued
7.
EN
A “High” input of 2.3V or higher to EN turns ON the VTT output. A “Low” input of 0.8V or less, on the other hand, turns
VTT to a Hi-Z state. With a “Low” EN input, however, the VREF output remains ON, provided that sufficient VCC and
VDDQ voltages have been established.
Absolute Maximum Ratings
Parameter
Input Voltage
Enable Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
Output Current
Power Dissipation1
Power Dissipation2
Power Dissipation3
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Symbol
V
CC
V
EN
V
VTT_IN
V
VDDQ
I
VTT
Pd1
Pd2
Pd3
Topr
Tstg
Tjmax
Rating
BD3538F
7
(Note 2) (Note 3)
7
(Note 2) (Note 3)
7
(Note 2) (Note 3)
7
(Note 2) (Note 3)
1
0.56
(Note 4)
0.69
(Note 5)
-
-40 to +105
-55 to +150
+150
BD3538HFN
7
(Note 2) (Note 3)
7
(Note 2) (Note 3)
7
(Note 2) (Note 3)
7
(Note 2) (Note 3)
1
0.63
(Note 6)
1.35
(Note 7)
1.75
(Note 8)
-40 to +105
-55 to +150
+150
Unit
V
V
V
V
A
W
W
W
°C
°C
°C
(Note 2) Should not exceed Pd.
(Note 3) Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.
(Note 4) Derate by 4.48mW/°C for Ta over 25°C (With no heat sink).
(Note 5) Derate by 5.52mW/°C for Ta over 25°C (When mounted on a board 70mm x 70mm x 1.6mm Glass-epoxyPCB).
(Note 6) Derate by 5.04mW/°C for Ta over 25°C (when mounted on a 70mm x 70mm x 1.6mm glass-epoxy board, 1-layer)
On less than 0.2% (percentage occupied by copper foil.
(Note 7) Derate by 10.8mW/°C for Ta over 25°C (when mounted on a 70mm x 70mm x 1.6mm glass-epoxy board, 1-layer)
On less than 7.0% (percentage occupied by copper foil.
(Note 8) Derate by 14.0mW/°C for Ta over 25°C (when mounted on a 70mm x 70mm x 1.6mm glass-epoxy board, 1-layer)
On less than 65.0% (percentage occupied by copper foil.
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all destructive situations such as
short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit protection measures, like adding a fuse, in case the IC is operated in a
special mode exceeding the absolute maximum ratings.
Recommended Operating Ratings
(Ta=25°C)
Parameter
Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
Enable Input Voltage
Symbol
V
CC
V
VTT_IN
V
VDDQ
V
EN
Rating
Min
2.7
1.0
1.0
-0.3
Max
5.5
5.5
2.75
+5.5
Unit
V
V
V
V
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BD3538F
BD3538HFN
Electrical Characteristics
(Unless otherwise noted, Ta=25°C V
CC
=3.3V V
EN
=3V V
VDDQ
=1.8V V
VTT_IN
=1.8V)
Limit
Parameter
Symbol
Min
Typ
Max
Standby Current
Bias Current
[Enable]
High Level Enable Input Voltage
Low Level Enable Input Voltage
Enable Pin Input Current
[Termination]
Termination Output Voltage 1
I
ST
I
CC
V
ENHIGH
V
ENLOW
I
EN
-
-
2.3
-0.3
-
0.5
2
-
-
7
1.0
4
5.5
+0.8
10
V
VREF
+30
m
V
VREF
+30
m
-
-1.0
50
40
0.9
0.9
0.8
0.8
Unit
mA
mA
V
V
µA
V
EN
=3V
I
VTT
=-1.0A to +1.0A
Ta=0°C to 105°C
(Note 9)
V
CC
=5V, V
VDDQ
=2.5V
V
VTT_IN
=2.5V
I
VTT
=-1.0A to +1.0A
Ta=0°C to 105°C
(Note 9)
V
EN
=0V
V
EN
=3V
Conditions
V
VTT1
V
VREF
-30m
V
VREF
V
Termination Output Voltage 2
Source Current
Sink Current
Load Regulation
Line Regulation
Upper Side ON-Resistance 1
Lower Side ON-Resistance 1
Upper Side ON-Resistance 2
Lower Side ON-Resistance 2
[Reference Voltage Input]
Input Impedance
Output Voltage 1
Output Voltage 2
V
VTT2
I
VTT+
I
VTT-
∆V
VTT
Reg.l
R
HRON1
R
LRON1
R
HRON2
R
LRON2
V
VREF
-30m
1.0
-
-
-
-
-
-
-
V
VREF
-
-
-
20
0.45
0.45
0.4
0.4
V
A
A
mV
mV
Ω
Ω
Ω
Ω
I
VTT
=-1.0A to +1.0A
V
CC
=5V, V
VDDQ
=2.5V
V
VTT_IN
=2.5V
V
CC
=5V, V
VDDQ
=2.5V
V
VTT_IN
=2.5V
Z
VDDQ
V
VREF1
V
VREF2
70
1/2 x V
VDDQ
-18m
1/2 x V
VDDQ
-40m
1/2 x V
VDDQ
-25m
1/2 x V
VDDQ
-40m
100
1/2 x
V
VDDQ
1/2 x
V
VDDQ
1/2 x
V
VDDQ
1/2 x
V
VDDQ
130
1/2 x
V
VDDQ
+18m
1/2 x
V
VDDQ
+40m
1/2 x
V
VDDQ
+25m
1/2 x
V
VDDQ
+40m
kΩ
V
V
I
REF
=-5mA to +5mA
Ta=0°C to 105°C
(Note 9)
I
REF
=-10mA to +10mA
Ta=0°C to 105°C
(Note 9)
V
CC
=5V, V
VDDQ
=2.5V
V
VTT_IN
=2.5V
I
VREF
=-5mA to +5mA
Ta=0°C to 105°C
(Note 9)
V
CC
=5V, V
VDDQ
=2.5V
V
VTT_IN
=2.5V
I
VTT
=-10mA to +10mA
Ta=0°C to 105°C
(Note 9)
VCC : sweep up
VCC : sweep down
Output Voltage 3
V
VREF3
V
Output Voltage 4
[UVLO]
Threshold Voltage
Hysteresis Voltage
(Note 9) No tested on outgoing inspection
V
VREF4
V
V
UVLO
∆V
UVLO
2.40
100
2.55
160
2.70
220
V
mV
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BD3538F
BD3538HFN
Typical Waveforms
V
VTT
(20mV/Div)
V
VTT
(20mV/Div)
I
VTT
(1A/Div)
I
VTT
(1A/Div)
10µsec/Div
10µsec/Div
Figure 1. DDR1
(-1A
→
+1A)
Figure 2. DDR1
(+1A
→
-1A)
V
VTT
(20mV/Div)
V
VTT
(20mV/Div)
I
VTT
(1A/Div)
I
VTT
(1A/Div)
10µsec/Div
10µsec/Div
Figure 3. DDR2
(-1A
→
+1A)
Figure 4. DDR2
(+1A
→
-1A)
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