EEWORLDEEWORLDEEWORLD

Part Number

Search

72V245L15TF8

Description
FIFO 3.3V 2KX18 SYNC FIFO
Categorystorage    storage   
File Size198KB,25 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

72V245L15TF8 Online Shopping

Suppliers Part Number Price MOQ In stock  
72V245L15TF8 - - View Buy Now

72V245L15TF8 Overview

FIFO 3.3V 2KX18 SYNC FIFO

72V245L15TF8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeTQFP
package instructionLFQFP, QFP64,.47SQ,20
Contacts64
Manufacturer packaging codePP64
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time10 ns
Other featuresEASILY EXPANDABLE IN DEPTH AND WIDTH
Maximum clock frequency (fCLK)66.7 MHz
period time15 ns
JESD-30 codeS-PQFP-G64
JESD-609 codee0
length10 mm
memory density73728 bit
Memory IC TypeOTHER FIFO
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals64
word count4096 words
character code4000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4KX18
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP64,.47SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.005 A
Maximum slew rate0.03 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width10 mm
Base Number Matches1
3.3 VOLT CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
IDT72V245
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
DESCRIPTION:
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
for a wide variety of data buffering needs, such as optical disk controllers, Local
Area Networks (LANs), and interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when
WEN
is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The Read Clock(RCLK) can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D0-D17
LD
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
WRITE CONTROL
LOGIC
FLAG
LOGIC
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
WRITE POINTER
FL
WXI
(HF)/WXO
RXI
RXO
RS
READ POINTER
READ CONTROL
LOGIC
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
OE
Q0-Q17
RCLK
REN
4294 drw 01
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
MARCH 2018
DSC-4294/8
©2018
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
USB Interface Technology (I)
I have been busy with the design of my graduation project recently, part of which involves USB communication. Since this is my first time to come into contact with USB low-level hardware design and so...
1234 RF/Wirelessly
Syntax of Timing Constraints in UCF Files
The most convenient and direct way to add constraints to a UCF file is to enter the timing constraints directly from the Constrains Editor. I have summarized the following commonly used syntaxes: [siz...
eeleader FPGA/CPLD
Tough Guy's DSP learning board, is this missing header file?
I just installed the built-in 28335 routine according to the tutorial, and an error occurred...
西里古1992 DSP and ARM Processors
Clearance sale of books, development boards, or exchanges, first round
[table=98%] [tr][td][align=center][color=rgb(153, 153, 153)][size=12px]This post was last edited by shamowangzi on 2013-8-24 15:00[/size][/color][/align] Please give me your contact QQ: 343675038. Som...
wuyanyanke Buy&Sell
Audio Codec Principle
[size=4]There are three common implementation schemes for audio codec. [/size] [size=4] [/size] [size=4] The first is to use a dedicated audio chip to collect and process voice signals, and the audio ...
fish001 Analogue and Mixed Signal
I've graduated, so I'm selling my MCU learning development board.
I'm graduating now, so I'm selling my MCU learning development board. Please cherish it . It's only 50 yuan....
axx123 51mcu

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1232  605  1357  478  2656  25  13  28  10  54 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号