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8SLVP2102ANLGI/W

Description
Clock Drivers & Distribution Dual 1:2 LVPECL Out Fanout Buffer
Categorylogic    logic   
File Size847KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

8SLVP2102ANLGI/W Overview

Clock Drivers & Distribution Dual 1:2 LVPECL Out Fanout Buffer

8SLVP2102ANLGI/W Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionHQCCN, LCC16,.12SQ,20
Contacts16
Manufacturer packaging codeNLG16P2
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionVFQFN- N 3 X 3 X 1.0 MM - NO LEAD
Other featuresALSO OPERATES AT 3.3 V SUPPLY
series8SLVP
Input adjustmentDIFFERENTIAL
JESD-30 codeS-XQCC-N16
JESD-609 codee3
length3 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions2
Number of inverted outputs
Number of terminals16
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHQCCN
Encapsulate equivalent codeLCC16,.12SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Sup0.225 ns
propagation delay (tpd)0.225 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.015 ns
Maximum seat height1.05 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width3 mm
Low Phase Noise, Dual 1-to-2, 3.3V,
2.5V LVPECL Output Fanout Buffer
8SLVP2102
Datasheet
Description
The 8SLVP2102 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP2102 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP2102 ideal for those clock distribution applications
demanding well-defined performance and repeatability.
Two selectable differential inputs and four low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
Two low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
Output skew: 5ps (typical)
Propagation delay: 225ps (maximum)
Low additive phase jitter, RMS, f
REF
= 156.25MHz, V
PP
= 1V,
12kHz – 20MHz: 36fs (maximum)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (I
EE
): 56mA (maximum)
Available in lead-free (RoHS 6), 16-Lead VFQFPN package
-40°C to 85°C ambient operating temperature
Supports case temperature ≤105°C operations
Accepts single-ended LVCMOS levels. See Applications section
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Pin Assignment
nQA1
nQA0
QA1
QA0
12 11 10
QB0
13
nQB0
14
QB1
15
nQB1
16
Block Diagram
V
CC
8
7
6
5
V
REF
nPCLKA
PCLKA
V
CC
9
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
1
V
EE
2
nc
3
PCLKB
4
nPCLKB
V
CC
8SLVP2102
16-Lead VFQFPN
3.0mm x 3.0mm x 0.925mm package body
NL Package
Top View
PCLKB
nPCLKB
QB0
nQB0
QB1
nQB1
Voltage
Reference
V
REF
©2018 Integrated Device Technology, Inc.
1
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