EiceDRIVER™
2EDN752x / 2EDN852x
Features
Fast, precise, strong and compatible
•
•
•
•
Highly efficient SMPS enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast MOSFET
and GaN switching
1 ns channel-to-channel propagation delay accuracy enables safe use of two channels in parallel
Two independent 5 A channels enable numerous deployment options
Industry standard packages and pinout ease system-design upgrades
The new Reference in Ruggedness
•
•
•
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal
conditions
-10 V control and enable input robustness delivers crucial safety margin when driving pulse-transformers or
driving MOSFETs in through hole packaging
5 A reverse current robustness eliminates the need for output protection circuitry.
Typical Applications
•
•
•
•
•
•
•
•
Server SMPS
TeleCom SMPS
DC-to-DC Converter
Bricks
Power Tools
Industrial SMPS
Motor Control
Solar SMPS
Example Topologies
•
•
•
Single and interleaved PFC
LLC, ZVS with pulse transformer
Synchronous Rectification
Description
The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level MOSFETs
and supports OptiMOS
TM
, CoolMOS
TM
, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and
GaN Power devices.
Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev. 2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Features
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to +20 V.
-10 V input pin robustness protects the driver against latch-up or electrical overstress which can be induced by
parasitic ground inductances. This greatly enhances system stability.
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under abnormal
conditions. Under such circumstances, this UVLO mechanism provides crucial independence from whether and
when other supervisors circuitries detect abnormal conditions.
Each of the two outputs is able to sink and source 5 A currents utilizing a true rail-to-rail stage. This ensures very
low on resistance of 0.7
Ω
up to the positive and 0.55
Ω
down to the negative rail respectively. Very tight channel
to channel delay matching, typ. 1 ns, permits parallel use of two channels, leading to a source and sink capability
of 10 A. Industry leading reverse current robustness eliminates the need for Schottky diodes at the outputs and
reduces the bill-of-material.
The pinout of the 2EDN family is compatible with the industry standard. Two different control input options,
direct and inverted, offer high flexibility. Three package variants, DSO 8-pin, TSSOP 8-pin, WSON 8-pin, allow
optimization of PCB board space usage and thermal characteristics.
From Controller
2EDN752x /
2EDN852x
1
ENA
2
INA
3
3
GND
4
4
INB
VDD
Load1
Load2
ENB
8
8
M
1
R
g1
OUTA
7
6
VDD
6
5
OUTB
5
R
g2
M
2
C
VDD
Data Sheet
2
Rev. 2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
1.1
1.2
2
3
4
4.1
4.2
4.3
4.4
4.5
5
5.1
5.2
5.3
5.4
6
7
8
8.1
8.2
8.3
9
Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
11
12
13
13
13
14
15
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG-DSO-8-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG-TSSOP-8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG-WSON-8-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
3
Rev. 2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1
Product Versions
The 2EDN752x / 2EDN852x are available in 2 different logic, 2 different undervoltage lockout and 3 package
versions.
Table 1
Package
PG-DSO-8-60
4.2V
direct
2EDN7524F
2N7524AF
EiceDRIV
XXHYYWW
2N7523AF
EiceDRIV
XXHYYWW
2N8524AF
EiceDRIV
XXHYYWW
2N8523AF
EiceDRIV
XXHYYWW
2N7524
AR_XXX
HYYWW
2N7523
AR_XXX
HYYWW
2N8524
AR_XXX
HYYWW
2N8523
AR_XXX
HYYWW
2N7524
AG_XXX
HYYWW
Product Versions
Type.
UVLO
Control Input Part Number
IC Topside
Marking Code
inverted
2EDN7523F
8V
direct
2EDN8524F
inverted
2EDN8523F
PG-TSSOP-8-1
4.2V
direct
2EDN7524R
inverted
2EDN7523R
8V
direct
2EDN8524R
inverted
2EDN8523R
PG-WSON-8-3
4.2V
direct
2EDN7524G
inverted
2EDN7523G
2N7523
AG_XXX
HYYWW
Data Sheet
4
Rev. 2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1.1
•
•
Logic Versions
The 2 logic versions are indicated by the variable x in the product version 2EDNy52x:
x=3: inverting input logic
x=4: non-inverting / direct input logic
The logic relations between inputs, enable pins and outputs are given in
Table 2
for the inverting and non-
inverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective
input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage
lockout event, due to low voltage at V
DD
, causes the respective output to be low too, regardless of the input signal.
Functional description is shown in
Chapter 3
(
Block Diagram)
and
Chapter 4
(Input
Configurations).
Table 2
Inputs
ENA
x
L
H
H
L
L
H
H
H
H
ENB
x
L
L
L
H
H
H
H
H
H
INA
x
x
L
H
x
x
L
H
L
H
INB
x
x
x
x
L
H
L
L
H
H
UVLO
1)
active
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
Logic Table
Output Inverting
OUTA
L
L
H
L
L
L
H
L
H
L
OUTB
L
L
L
L
H
L
H
H
L
L
Output Standard
OUTA
L
L
L
H
L
L
L
H
L
H
OUTB
L
L
L
L
L
H
L
L
H
H
1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage.
Active means that UVLO disable active the output stages.
1.2
Package Versions
The logic and UVLO versions are available in 3 different packages.
•
•
•
a standard PG-DSO-8-60 (designated by “F”)
a small PG-TSSOP-8-1 (designated by “R”)
a leadless PG-WSON-8-3 (designated by “G”)
Drawings can be viewed in
Chapter 8
(Outline
Dimensions).
Data Sheet
5
Rev. 2.5
2018-04-20
京公网安备 11010802033920号
EEWORLD
