3.3V DS21352 and 5V DS21552
T1 Single-Chip Transceivers
www.maxim-ic.com
FEATURES
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Complete DS1/ISDN–PRI/J1 transceiver functionality
Long and Short haul LIU
Crystal–less jitter attenuator
Generates DSX–1 and CSU line build-outs
HDLC controller with 64-byte buffers Configurable for
FDL or DS0 operation
Dual two–frame elastic store slip buffers that can
connect to asynchronous backplanes up to 8.192MHz
8.192MHz clock output locked to RCLK
Interleaving PCM Bus Operation
Per-channel loopback and idle code insertion
8-bit parallel control port muxed or nonmuxed buses
(Intel or Motorola)
Programmable output clocks for Fractional T1
Fully independent transmit and receive functionality
Generates/detects in-band loop codes from 1 to 8 bits
in length including CSU loop codes
IEEE 1149.1 JTAG-Boundary Scan
Pin compatible with DS2152/54/354/554 SCTs
100-pin LQFP package (14 mm x 14 mm) 3.3V
(DS21352) or 5V (DS21552) supply; low power
CMOS
PIN ASSIGNMENT
DS21352
DS21552
100
1
ORDERING INFORMATION
DS21352L
DS21352LN
DS21552L
DS21552LN
(0°C to +70°C)
(-40°C to +85°C)
(0°C to +70°C)
(-40°C to +85°C)
DESCRIPTION
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1
lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of
internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12–90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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120501
DS21352/DS21552
TABLE OF CONTENTS
1.
2.
3.
LIST OF FIGURES .........................................................................................................................5
LIST OF TABLES ...........................................................................................................................6
INTRODUCTION............................................................................................................................7
3.1 FUNCTIONAL DESCRIPTION..............................................................................................8
3.2 DOCUMENT REVISION HISTORY....................................................................................10
PIN DESCRIPTION ......................................................................................................................11
4.1 PIN FUNCTION DESCRIPTION..........................................................................................17
4.1.1 Transmit Side Pins ........................................................................................................17
4.1.2 Receive Side Pins ..........................................................................................................20
4.1.3 Parallel Control Port Pins............................................................................................23
4.1.4 JTAG Test Access Port Pins .........................................................................................25
4.1.5 Interleave Bus Operation Pins......................................................................................25
4.1.6 Line Interface Pins ........................................................................................................26
4.1.7 Supply Pins....................................................................................................................27
PARALLEL PORT........................................................................................................................28
5.1 REGISTER MAP ...................................................................................................................28
CONTROL, ID, AND TEST REGISTERS .................................................................................32
6.1 POWER-UP SEQUENCE......................................................................................................32
6.2 DEVICE ID ............................................................................................................................32
6.3 PAYLOAD LOOPBACK.......................................................................................................37
6.4 FRAMER LOOPBACK .........................................................................................................38
6.5 PULSE DENSITY ENFORCER ............................................................................................40
6.6 REMOTE LOOPBACK .........................................................................................................44
STATUS AND INFORMATION REGISTERS..........................................................................45
ERROR COUNT REGISTERS ....................................................................................................52
8.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) ................................................53
8.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) ...............................................54
8.3 MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)....................................55
DSO MONITORING FUNCTION...............................................................................................56
4.
5.
6.
7.
8.
9.
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DS21352/DS21552
10.
11.
12.
13.
14.
15.
SIGNALING OPERATION..........................................................................................................58
10.1 PROCESSOR-BASED SIGNALING ....................................................................................58
10.2 HARDWARD-BASED SIGNALING ...................................................................................60
10.2.1 Receive Side.................................................................................................................60
10.2.2 Transmit Side...............................................................................................................61
PER-CHANNEL CODE (IDLE) GENERATION ......................................................................61
11.1 TRANSMIT SIDE CODE GENERATION ...........................................................................62
11.1.1 Fixed Per-Channel Idle Code Insertion ......................................................................62
11.1.2 Unique Per-Channel Idle Code Insertion....................................................................63
11.2 RECEIVE SIDE CODE GENERATION...............................................................................63
11.2.1 Fixed Per-Channel Idle Code Insertion ......................................................................64
11.2.3 Unique Per-Channel Idle Code Insertion....................................................................64
PER-CHANNEL LOOPBACK.....................................................................................................65
CLOCK BLOCKING REGISTERS ............................................................................................65
ELASTIC STORES OPERATION ..............................................................................................66
14.1 RECEIVE SIDE .....................................................................................................................66
14.2 TRANSMIT SIDE..................................................................................................................67
14.3 ELASTIC STORES INITIALIZATION ................................................................................67
14.4 MINIMUM DELAY MODE..................................................................................................67
HDLC CONTROLLER.................................................................................................................68
15.1 HDLC FOR DS0S ..................................................................................................................68
15.1.1 Receive an HDLC Message .........................................................................................68
15.1.2 Transmit an HDLC Message .......................................................................................68
15.2 FDL/Fs EXTRACTION AND INSERTION .........................................................................69
15.3 HDLC and BOC CONTROLLER FOR THE FDL................................................................69
15.3.1 General Overview........................................................................................................69
15.3.2 Status Register for the HDLC......................................................................................70
15.3.3 Basic Operation Details ..............................................................................................71
15.3.4 HDLC/BOC Register Description ...............................................................................72
15.4 LEGACY FDL SUPPORT.....................................................................................................82
15.4.1 Overview......................................................................................................................82
15.4.2 Receive Section ............................................................................................................82
15.4.3 Transmit Section ..........................................................................................................84
15.5 D4/SLC-96 OPERATION......................................................................................................84
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16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
LINE INTERFACE FUNCTION .................................................................................................85
16.1 RECEIVE CLOCK AND DATA RECOVERY ....................................................................85
16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING.......................................................86
16.3 JITTER ATTNUATOR..........................................................................................................86
16.4 PROTECTED INTERFACES................................................................................................92
16.5 RECEIVE MONITOR MODE...............................................................................................95
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............96
TRANSMIT TRANSPARENCY ..................................................................................................99
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................99
19.1 DESCRIPTION ......................................................................................................................99
19.2 TAP CONTROLLER STATE MACHINE ..........................................................................101
19.3 INSTRUCTION REGISTER ...............................................................................................103
19.4 TEST REGISTERS ..............................................................................................................105
INTERLEAVED PCM BUS OPERATION ..............................................................................109
20.1 CHANNEL INTERLEAVE .................................................................................................111
20.2 FRAME INTERLEAVE.......................................................................................................111
FUNCTIONAL TIMING DIAGRAMS .....................................................................................111
RECEIVE AND TRANSMIT DATA FLOW DIAGRAMS.....................................................123
OPERATING PARAMETERS...................................................................................................125
AC TIMING PARAMETERS AND DIAGRAMS....................................................................126
24.1 MULTIPLEXED BUS AC CHARACTERISTICS .............................................................126
24.2 NON-MULTIPLEXED BUS AC CHARACTERISTICS ...................................................129
24.3 RECEIVE SIDE AC CHARACTERISTICS .......................................................................132
24.4 TRANSMIT AC CHARACTERISTICS..............................................................................136
MECHANICAL DESCRIPTTION ............................................................................................139
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DS21352/DS21552
1. LIST OF FIGURES
Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9
Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87
Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88
Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89
Figure 16-4 JITTER TOLERANCE .........................................................................................................91
Figure 16-5 JITTER ATTENUATION ....................................................................................................91
Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93
Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94
Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95
Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100
Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103
Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110
Figure 21-1 RECEIVE SIDE D4 TIMING.............................................................................................111
Figure 21-2 RECEIVE SIDE ESF TIMING...........................................................................................112
Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)..............................113
Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ...........113
Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ...........114
Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE ..............................115
Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE ...........................116
Figure 21-8 TRANSMIT SIDE D4 TIMING .........................................................................................117
Figure 21-9 TRANSMIT SIDE ESF TIMING .......................................................................................118
Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) ........................119
Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)......119
Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)......120
Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE.........................121
Figure 21-14 TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE .....................122
Figure 22-1 RECEIVE DATA FLOW ...................................................................................................123
Figure 22-2 TRANSMIT DATA FLOW................................................................................................124
Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX=1) .............................................................127
Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...........................................................127
Figure 24-3 MOTOROLA BUS TIMING (BTS=1 / MUX=1)..............................................................128
Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) ..............................................................130
Figure 24-5 INTEL BUS READ TIMING (BTS=0 / MUX=0) .............................................................130
Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-7 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-8 RECEIVE SIDE TIMING ..................................................................................................133
Figure 24-9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED...............................................134
Figure 24-10 RECEIVE LINE INTERFACE TIMING .........................................................................135
Figure 24-11 TRANSMIT SIDE TIMING.............................................................................................137
Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED .........................................138
Figure 24-13 TRANSMIT LINE INTERFACE TIMING......................................................................138
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