dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to
2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS
Advanced Analog Features (Continued)
• Up to Four High-Speed Comparators with Direct
Connection to the PWM module:
- Programmable references with 1024 voltage points
Core: 16-Bit dsPIC33F CPU
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Timers/Output Compare/Input Capture
• Three General Purpose Timers:
- Three 16-bit and one 32-bit timer/counter
• Two Output Compare (OC) modules
• Two Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow Function Remap
Clock Management
•
•
•
•
•
±2.0% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Communication Interfaces
• UART module (12.5 Mbps):
- With support for LIN/J2602 protocols and IrDA
®
• 4-Wire SPI module
• I
2
C™ module (up to 1 Mbaud) with SMBus Support
• PPS to allow Function Remap
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
Input/Output
• Sink/Source 18 mA on 8 Pins, 10 mA on 10 Pins
and 6 mA on 17 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• External Interrupts on up to 30 I/O Pins
High-Speed PWM
Up to Four PWM Pairs with Independent Timing
Dead Time for Rising and Falling Edges
1.04 ns PWM Resolution
PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
•
•
•
•
Qualification and Class B Support
•
•
•
•
AEC-Q100 REVG (Grade 1, -40ºC to +125ºC)
AEC-Q100 REVG (Grade 0, -40ºC to +150ºC)
Class B Safety Library, IEC 60730, VDE Certified
6x6x0.5 mm UQFN Package Designed and
Optimized to ease IPC9592A 2nd Level Temperature
Cycle Qualification
Advanced Analog Features
• ADC module:
- 10-bit resolution with up to 2 Successive Approximation
Register (SAR) converters (4 Msps) and up to
six Sample-and-Hold (S&H) circuits
- Up to 12 input channels grouped into six conversion
pairs, plus two voltage reference monitoring inputs
- Dedicated result buffer for each analog channel
• Flexible and Independent ADC Trigger Sources
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Two Breakpoints
IEEE 1149.2-Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
2008-2014 Microchip Technology Inc.
DS70000318G-page 1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
dsPIC33FJ06GS101/X02 AND
dsPIC33FJ16GSX02/X04 PRODUCT
FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
TABLE 1:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CONTROLLER FAMILIES
Program Flash Memory (Kbytes)
Remappable Peripherals
ADC
Sample-and-Hold (S&H) Circuit
Analog-to-Digital Inputs
External Interrupts
(3)
Analog Comparator
Remappable Pins
RAM (Bytes)
Output Compare
DAC Output
Input Capture
16-Bit Timer
UART
dsPIC33FJ06GS101
dsPIC33FJ06GS102
18
28
6
6
256
256
8
16
2
2
0
0
1
1
1
1
1
1
2x2
(1)
2x2
0
0
3
3
0
0
1
1
SARs
SPI
Device
PWM
(2)
1
1
3
3
6
6
13
21
SOIC
SPDIP,
SOIC,
QFN-S
SPDIP,
SOIC,
QFN-S
SPDIP,
SOIC,
QFN-S
QFN,
TQFP,
VTLA
SPDIP,
SOIC,
QFN-S,
UQFN
QFN,
TQFP,
VTLA
dsPIC33FJ06GS202
28
6
1K
16
2
1
1
1
1
2x2
2
3
1
1
1
3
6
21
dsPIC33FJ16GS402
28
16
2K
16
3
2
2
1
1
3x2
0
3
0
1
1
4
8
21
dsPIC33FJ16GS404
44
16
2K
30
3
2
2
1
1
3x2
0
3
0
1
1
4
8
35
dsPIC33FJ16GS502
28
16
2K
16
3
2
2
1
1
4x2
(1)
4
3
1
1
2
6
8
21
dsPIC33FJ16GS504
44
16
2K
30
3
2
2
1
1
4x2
(1)
4
3
1
1
2
6
12
35
Note 1:
2:
3:
The PWM4H:PWM4L pins are remappable.
The PWM Fault pins and PWM synchronization pins are remappable.
Only two out of three interrupts are remappable.
DS70000318G-page 2
2008-2014 Microchip Technology Inc.
Packages
I/O Pins
I
2
C™
Pins
FPGA/CPLD
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