DS3142N datasheet, PDF - EEWORLD Datasheet

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DS3142N: DescriptionTelecom Interface ICs Dual DS3/E3 Framer; CategoryWireless rf/communication Telecom circuit; File Size1MB，88 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS3142N Overview

Telecom Interface ICs Dual DS3/E3 Framer

DS3142N Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	13 X 13 MM, CSBGA-144
Contacts	144
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	1 week
JESD-30 code	S-PBGA-B144
length	13 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.75 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	FRAMER
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	13 mm
Base Number Matches	1

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DESIGN KIT AVAILABLE

DS3141/DS3142/DS3143/DS3144

Single/Dual/Triple/Quad

DS3/E3 Framers

www.maxim-ic.com

GENERAL DESCRIPTION

The DS3141, DS3142, DS3143, and DS3144

(DS314x) devices include all necessary circuitry to

frame and format up to four separate DS3 or E3

channels. Each framer in these devices is

independently configurable to support M23 DS3,

C-Bit Parity DS3, or G.751 E3. The framers interface

to a variety of line interface units (LIUs),

microprocessor

buses,

and

other

system

components without glue logic. Each DS3/E3 framer

has its own HDLC controller, FEAC controller, and

BERT, as well as full support for error detection and

generation, performance monitoring, and loopbacks.

FEATURES

One/Two/Three/Four Independent DS3/E3

Framers on a Single Die

Framing and Formatting to M23 DS3, C-Bit Parity

DS3, and G.751 E3

LIU Interface can be Binary (NRZ) or Dual-Rail

(POS/NEG)

B3ZS/HDB3 Encoder and Decoder

Generate and Detect DS3/E3 Alarms

Integrated HDLC Controller for Each Channel

Integrated FEAC Controller for Each Channel

Integrated Bit Error-Rate Tester (BERT) for Each

Channel

Large Performance-Monitoring Counters

Line, Diagnostic, and Payload Loopbacks

Externally Controlled Transmit Overhead

Insertion Port

Support External Timing or Loop-Timing

Framers can be Powered Down When Not Used

8-Bit Processor Port Supports Muxed or

Nonmuxed Bus Operation (Intel or Motorola)

3.3V Supply with 5V Tolerant I/O

144-Pin, 13mm x 13mm CSBGA Package

IEEE 1149.1 JTAG Support

APPLICATIONS

SONET/SDH Muxes

PDH Muxes

Digital Cross-Connect Systems

Access Concentrators

ATM and Frame Relay Equipment

Routers

FUNCTIONAL DIAGRAM

LIU

INTERFACE

POS/NRZ

NEG

CLK

POS/NRZ

NEG/LCV

CLK

EACH FRAMER

SYSTEM

INTERFACE

CLK

DATA

SYNC

OVERHEAD

CLK

DATA

SYNC

Dallas

Semiconductor

DS314x

TRANSMIT

FORMATTER

RECEIVE

FRAMER

ORDERING INFORMATION

PART

DS3141

DS3141N

DS3142

DS3143

DS3143N

DS3144

DS3144N

NO. OF

FRAMERS

TEMP RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

144 CSBGA

Pin Configurations appear at end of data sheet.

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

1 of 88

REV: 012003

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

7.10.2

7.10.3

Transmit Operation .............................................................................................................................. 54

HDLC Register Description .................................................................................................................. 54

7.11

7.11.1

FEAC C

ONTROLLER

............................................................................................................... 62

FEAC Register Description .................................................................................................................. 63

OPERATION DETAILS ................................................................................................................. 67

8.1

8.2

8.3

8.4

8.5

ESET

....................................................................................................................................... 67

DS3

AND

E3 M

ODE

ONFIGURATION

.......................................................................................... 67

LIU

AND

YSTEM

NTERFACE

ONFIGURATION

............................................................................. 67

OOPBACK

ODES

..................................................................................................................... 68

RANSMIT

VERHEAD

NSERTION

................................................................................................ 68

JTAG TAP C

ONTROLLER

TATE

ACHINE

.................................................................................. 69

JTAG I

NSTRUCTION

EGISTER AND

NSTRUCTIONS

...................................................................... 71

JTAG S

CAN

EGISTERS

............................................................................................................. 72

JTAG INFORMATION ................................................................................................................... 69

9.1

9.2

9.3

10. DC ELECTRICAL CHARACTERISTICS ....................................................................................... 73

11. AC TIMING CHARACTERISTICS ................................................................................................. 74

11.1

11.2

11.3

YSTEM

NTERFACE

IMING

..................................................................................................... 74

ICROPROCESSOR

NTERFACE

IMING

..................................................................................... 76

JTAG I

NTERFACE

IMING

........................................................................................................ 81

12. PIN ASSIGNMENTS ..................................................................................................................... 82

13. PACKAGE INFORMATION........................................................................................................... 87

14. THERMAL INFORMATION ........................................................................................................... 88

15. REVISION HISTORY..................................................................................................................... 88

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

LIST OF FIGURES

Figure 1-1. Block Diagram ....................................................................................................................... 6

Figure 2-1. Application Example: 12-Port Unchannelized DS3/E3 Card .................................................. 6

Figure 5-1. Transmit Formatter Timing .................................................................................................. 11

Figure 5-2. Receive Framer Timing ....................................................................................................... 13

Figure 6-1. Status Register Interrupt Flow ............................................................................................. 17

Figure 7-1. Transmit Data Block Diagram.............................................................................................. 18

Figure 7-2. Transmit Clock Block Diagram ............................................................................................ 19

Figure 7-3. Receiver Block Diagram ...................................................................................................... 19

Figure 7-4. MSR Status Bit Interrupt Signal Flow................................................................................... 31

Figure 7-5. T3E3SR Status Bit Interrupt Signal Flow ............................................................................. 39

Figure 7-6. BERT Status Bit Interrupt Signal Flow ................................................................................. 50

Figure 7-7. HDLC Status Bit Interrupt Signal Flow................................................................................. 59

Figure 7-8. FEAC Status Bit Interrupt Signal Flow ................................................................................. 65

Figure 9-1. JTAG Block Diagram ........................................................................................................... 69

Figure 9-2. JTAG TAP Controller State Machine ................................................................................... 70

Figure 11-1. Data Path Timing Diagram ................................................................................................ 75

Figure 11-2. Line Loopback Timing Diagram ......................................................................................... 75

Figure 11-3. SCLK Clock Timing ........................................................................................................... 76

Figure 11-4. Microprocessor Interface Timing Diagram (Nonmultiplexed).............................................. 77

Figure 11-5. Microprocessor Interface Timing Diagram (Multiplexed) .................................................... 79

Figure 11-6. JTAG Interface Timing Diagram ........................................................................................ 81

Figure 12-1. DS3141 Pin Configuration ................................................................................................. 83

Figure 12-2. DS3142 Pin Configuration ................................................................................................. 84

Figure 12-3. DS3143 Pin Configuration ................................................................................................. 85

Figure 12-4. DS3144 Pin Configuration ................................................................................................. 86

4 of 88

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

LIST OF TABLES

Table 4-A. Applicable Telecommunications Standards ............................................................................ 8

Table 6-A. Register Map........................................................................................................................ 15

Table 6-B. Status Register Set Example................................................................................................ 17

Table 7-A. BERT/Loopback Interaction—Payload Bits .......................................................................... 20

Table 7-B. BERT/Loopback Interaction—Overhead Bits........................................................................ 21

Table 7-C. Common Line Interface Register Map.................................................................................. 22

Table 7-D. DS3/E3 Framer Register Map .............................................................................................. 32

Table 7-E. DS3 Alarm Criteria ............................................................................................................... 40

Table 7-F. E3 Alarm Criteria .................................................................................................................. 40

Table 7-G. BERT Register Map ............................................................................................................. 45

Table 7-H. HDLC Register Map ............................................................................................................. 54

Table 7-I. FEAC Register Map............................................................................................................... 63

Table 9-A. JTAG Instruction Codes ....................................................................................................... 71

Table 9-B. JTAG ID Code...................................................................................................................... 72

Table 10-A. Recommended DC Operating Conditions........................................................................... 73

Table 10-B. DC Electrical Characteristics .............................................................................................. 73

Table 11-A. Data Path Timing ............................................................................................................... 74

Table 11-B. Line Loopback Timing ........................................................................................................ 74

Table 11-C. Microprocessor Interface Timing ........................................................................................ 76

Table 11-D. JTAG Interface Timing ....................................................................................................... 81

Table 12-A. Pin Assignments (Sorted by Signal Name)......................................................................... 82

Table 14-A. Thermal Properties, Natural Convection............................................................................. 88

Table 14-B. Theta-JA (q

) vs. Airflow.................................................................................................... 88

5 of 88

DS3142N Related Products

	DS3142N	DS3143	DS3141	DS3143N	DS3142+
Description	Telecom Interface ICs Dual DS3/E3 Framer	Telecom Interface ICs Triple DS3/E3 Framer	Telecom Interface ICs Single DS3/E3 Framer	Telecom Interface ICs Triple DS3/E3 Framer	Telecom Interface ICs
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Lead free
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	conform to
package instruction	13 X 13 MM, CSBGA-144	13 X 13 MM, CSBGA-144	13 X 13 MM, CSBGA-144	13 X 13 MM, CSBGA-144	13 X 13 MM, CSBGA-144
Reach Compliance Code	compliant	not_compliant	not_compliant	not_compliant	compliant
JESD-30 code	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144
length	13 mm	13 mm	13 mm	13 mm	13 mm
Number of functions	1	1	1	1	1
Number of terminals	144	144	144	144	144
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	240	240	240	240	NOT SPECIFIED
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
Telecom integrated circuit types	FRAMER	FRAMER	FRAMER	FRAMER	FRAMER
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20	NOT SPECIFIED
width	13 mm	13 mm	13 mm	13 mm	13 mm
Parts packaging code	BGA	BGA	BGA	BGA	-
Contacts	144	144	144	144	-
ECCN code	EAR99	EAR99	EAR99	-	-
Humidity sensitivity level	3	3	3	3	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Base Number Matches	1	1	-	1	1
JESD-609 code	-	e0	e0	e0	-
Encapsulate equivalent code	-	BGA144,12X12,40	BGA144,12X12,40	BGA144,12X12,40	-
power supply	-	3.3 V	3.3 V	3.3 V	-
Maximum slew rate	-	0.25 mA	0.09 mA	0.25 mA	-
technology	-	BIPOLAR	BIPOLAR	BIPOLAR	-
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-

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