Data Sheet
FEATURES
Super Sequencer with Margining Control
and Auxiliary ADC Inputs
ADM1066
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN
REFOUT REFGND
SDA SCL A1
A0
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage-margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
ADM1066
MUX
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
EEPROM
CLOSED-LOOP
MARGINING SYSTEM
VX1
VX2
VX3
VX4
VX5
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
VP1
VP2
VP3
VP4
VH
AGND
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
VDD
ARBITRATOR
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
04609-001
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
VCCP GND
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The
ADM1066
Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple-supply systems. In addition
to these functions, the
ADM1066
integrates a 12-bit ADC and
six 8-bit voltage output DACs. These circuits can be used to
implement a closed-loop margining system that enables supply
adjustment by altering either the feedback node or reference of
a dc-to-dc converter using the DAC outputs.
Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit testing
of a board during production (for example, to verify board func-
tionality at −5% of nominal supplies), or it can be used dynamically
to accurately control the output voltage of a dc-to-dc converter.
For more information about the
ADM1066
register map,
refer to the
AN-698 Application Note.
Rev. F
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ADM1066
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Detailed Block Diagram .................................................................. 4
Specifications..................................................................................... 5
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Powering the ADM1066 ................................................................ 14
Slew Rate Consideration ............................................................ 14
Inputs ................................................................................................ 15
Supply Supervision ..................................................................... 15
Programming the Supply Fault Detectors ............................... 15
Input Comparator Hysteresis .................................................... 15
Input Glitch Filtering ................................................................. 16
Supply Supervision with VXx Inputs ....................................... 16
VXx Pins as Digital Inputs ........................................................ 17
Outputs ............................................................................................ 18
Supply Sequencing Through Configurable Output Drivers . 18
Default Output Configuration .................................................. 18
Sequencing Engine ......................................................................... 19
Overview...................................................................................... 19
Data Sheet
Warnings...................................................................................... 19
SMBus Jump (Unconditional Jump) ........................................ 19
Sequencing Engine Application Example ............................... 20
Fault and Status Reporting ........................................................ 21
Voltage Readback............................................................................ 22
Supply Supervision with the ADC ........................................... 22
Supply Margining ........................................................................... 23
Overview ..................................................................................... 23
Open-Loop Supply Margining ................................................. 23
Closed-Loop Supply Margining ............................................... 23
Writing to the DACs .................................................................. 24
Choosing the Size of the Attenuation Resistor ....................... 24
DAC Limiting and Other Safety Features ............................... 24
Applications Diagram .................................................................... 25
Communicating with the ADM1066 ........................................... 26
Configuration Download at Power-Up ................................... 26
Updating the Configuration ..................................................... 26
Updating the Sequencing Engine ............................................. 27
Internal Registers........................................................................ 27
EEPROM ..................................................................................... 27
Serial Bus Interface..................................................................... 27
SMBus Protocols for RAM and EEPROM .............................. 29
Write Operations ........................................................................ 29
Read Operations ......................................................................... 31
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 33
Rev. F | Page 2 of 36
Data Sheet
REVISION HISTORY
1/15—Rev. E to Rev. F
Changed Round-Robin Circuit to
ADC Round-Robin ....................................................... Throughout
Changes to Figure 3, Figure 4, and Table 4 .................................... 9
Added Slew Rate Consideration Section ......................................14
Added VP1 Glitch Filtering Section .............................................16
Added SCL Held Low Timeout Section and False Start
Detection Section ............................................................................28
Updated Outline Dimensions ........................................................33
Changes to Ordering Guide ...........................................................33
6/11—Rev. D to Rev. E
Changes to Serial Bus Timing Parameter in Table 1 .................... 5
Changes to Figure 3........................................................................... 9
Added Exposed Pad Notation to Outline Dimensions ..............31
Changes to Ordering Guide ...........................................................31
5/08—Rev. C to Rev. D
Changes to Powering the ADM1066 Section ..............................14
Changes to Table 5 ..........................................................................15
Changes to Default Output Configuration Section ....................17
Changes to Sequence Detector Section ........................................19
Changes to Configuration Download at Power-Up Section .....25
Changes to Table 11 ........................................................................26
Changes to Figure 36 ......................................................................27
Changes to Figure 37 ......................................................................28
Changes to Figure 46 and Error Correction Section ..................30
Changes to Ordering Guide ...........................................................31
11/06—Rev. B to Rev. C
Updated Format.................................................................. Universal
Changes to Features .......................................................................... 1
Changes to Figure 2........................................................................... 3
Changes to Buffered Voltage Output DACs .................................. 5
Changes to Table 2 ............................................................................ 7
Changes to Table 6 ..........................................................................14
Changes to Programming the Supply Fault Detectors Section .14
Changes to Table 9 ..........................................................................22
Changes to Figure 36 and Figure 37 .............................................29
ADM1066
5/06—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 8
Changes to Table 3 .......................................................................... 10
Added Table 4 .................................................................................. 10
Added Default Output Configuration Section............................ 19
Changes to Fault Reporting Section ............................................. 19
Added Table 11 ................................................................................ 30
Changes to Ordering Guide ........................................................... 36
1/05—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Absolute Maximum Ratings Section ......................... 8
Change to Supply Sequencing Through Configurable
Output Drivers Section .................................................................. 16
Changes to Figure 33 ...................................................................... 23
Change to Table 10 .......................................................................... 32
10/04—Revision 0: Initial Version
Rev. F | Page 3 of 36
ADM1066
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs
can also provide up to a 12 V output for driving the gate of an N-
FET that can be placed in the path of a supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
Data Sheet
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
REFIN REFOUT
AUX2 AUX1
REFGND SDA SCL A1
A0
ADM1066
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
OSC
DEVICE
CONTROLLER
EEPROM
GPI SIGNAL
CONDITIONING
VX1
VX2
VX3
VX4
GPI SIGNAL
CONDITIONING
VX5
SEQUENCING
ENGINE
SFD
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
PDO2
PDO3
PDO4
PDO5
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO6
VP1
VP2
VP3
VP4
VH
SFD
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO7
PDO8
PDO9
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO10
PDOGND
AGND
VDDCAP
VDD
ARBITRATOR
REG 5.25V
CHARGE PUMP
V
OUT
DAC
V
OUT
DAC
GND
VCCP
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
Figure 2. Detailed Block Diagram
Rev. F | Page 4 of 36
04609-002
Data Sheet
SPECIFICATIONS
VH = 3.0 V to 14.4 V
1
, VPx = 3.0 V to 6.0 V
1
, T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
C
VDDCAP
POWER SUPPLY
Supply Current, I
VH
, I
VPx
Additional Currents
All PDO FET Drivers On
Current Available from
VDDCAP
DAC Supply Currents
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Range
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
ANALOG-TO-DIGITAL CONVERTER
Signal Range
Min
3.0
6.0
14.4
5.4
Typ
Max
Unit
V
V
V
V
µF
mA
mA
2
2.2
1
10
mA
mA
mA
mA
Test Conditions/Comments
ADM1066
2.7
10
4.75
Minimum supply required on one of VPx, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 µA each,
PDO7 to PDO10 off
Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
Six DACs on with 100 µA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
4.2
1
6
52
±0.05
6
2.5
52
±0.05
2.5
1.25
0.573
1
0.573
1.375
±1
8
0
100
0
V
REFIN
6
3
1.375
14.4
6
kΩ
%
V
V
kΩ
%
V
V
V
MΩ
V
%
Bits
µs
µs
V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error + input
attenuation error
Minimum programmable filter length
Maximum programmable filter length
The ADC can convert signals presented to the VH, VPx, and VXx
pins; VPx and VH input signals are attenuated depending on the
selected range; a signal at the pin corresponding to the selected
range is from 0.573 V to 1.375 V at the ADC input
Input Reference Voltage on
REFIN Pin, V
REFIN
Resolution
INL
Gain Error
2.048
12
±2.5
±0.05
V
Bits
LSB
%
Endpoint corrected, V
REFIN
= 2.048 V
V
REFIN
= 2.048 V
Rev. F | Page 5 of 36
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