NCV51411
1.5 A, 260 kHz, Low Voltage
Buck Regulator with
Synchronization Capability
The NCV51411 is a 1.5 A buck regulator IC operating at a
fixed−frequency of 260 kHz. The device uses the V
2
t
control
architecture to provide unmatched transient response, the best overall
regulation and the simplest loop compensation for today’s high−speed
logic. The NCV51411 accommodates input voltages from 4.5 V to
40 V and contains synchronization circuitry.
The on−chip NPN transistor is capable of providing a minimum of
1.5 A of output current, and is biased by an external “boost” capacitor
to ensure saturation, thus minimizing on−chip power dissipation.
Protection circuitry includes thermal shutdown, cycle−by−cycle
current limiting and frequency foldback. The NCV51411 is
functionally pin−compatible with the LT1375.
Features
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MARKING
DIAGRAMS
SO−8
D SUFFIX
CASE 751
8
51411
ALYWE
G
1
8
1
16
16
1
1
SO−16W EP
PW SUFFIX
CASE 751AG
NCV51411
AWLYYWWG
•
V
2
Architecture Provides Ultra−Fast Transient Response, Improved
•
•
•
•
•
•
•
•
•
•
•
Regulation and Simplified Design
2.0% Error Amp Reference Voltage Tolerance
Switch Frequency Decrease of 4:1 in Short Circuit Conditions
Reduces Short Circuit Power Dissipation
BOOST Lead Allows “Bootstrapped” Operation to Maximize
Efficiency
Sync Function for Parallel Supply Operation or Noise Minimization
Shutdown Pin Provides Power−Down Option
85
mA
Quiescent Current During Power−Down
Thermal Shutdown
Soft−Start
Pin Compatible with LT1375 (SO−8 Version)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
18
1
NCV51411
AWLYYWW
G
G
18
1
18−LEAD DFN
MN SUFFIX
CASE 505
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
E
= Automotive Grade
G
or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 16
1
Publication Order Number:
NCV51411/D
NCV51411
D1
4.5 V
−
16 V
C2
100
mF
Shutdown
SYNC
4
5
U1 2
V
IN
SHDNB
SYNC
V
C
8
C4
0.1
mF
1
BOOST
NCV51411
GND
6
V
FB
7
V
SW
3
L1
15
mH
D3
1N5821
R1
205
C1
0.1
mF
3.3 V
1N4148
C3
100
mF
R2
127
Figure 1. Application Diagram, 4.5 V
−
16 V to 3.3 V @ 1.0 A Converter
MAXIMUM RATINGS*
Rating
Peak Transient Voltage (31 V Load Dump @ V
IN
= 14 V)
Operating Junction Temperature Range, T
J
Lead Temperature Soldering:
Storage Temperature Range, T
S
ESD
(Human Body Model)
(Machine Model)
(Charge Device Model)
SO−8 Junction−to−Case, R
qJC
SO−8 Junction−to−Ambient, R
qJA
SO−16 Junction−to−Case, R
qJC
SO−16 Junction−to−Ambient, R
qJA
(Note 3)
18−Lead DFN Junction−to−Ambient, R
qJA
(Note 3)
Reflow: (Note 1)
Value
45
−40
to 150
240 peak
(Note 2)
−65
to +150
2.0
200
>1.0
45
165
16
35
38
Unit
V
°C
°C
°C
kV
V
kV
°C/W
°C/W
°C/W
°C/W
°C/W
Package Thermal Resistance
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. 60 second maximum above 183°C.
2.
−5°C/0°C
allowable conditions.
3. 4 layer board, 1 oz copper outer layers, 0.5 oz copper inner layers, 600 sqmm copper area
MAXIMUM RATINGS
(Voltages are with respect to GND)
Pin Name
V
IN
(DC)*
BOOST
V
SW
V
C
SHDNB
SYNC
V
FB
*See table above for load dump.
V
Max
40 V
40 V
40 V
7.0 V
7.0 V
7.0 V
7.0 V
V
MIN
−0.3
V
−0.3
V
−0.6
V/−1.0 V, t < 50 ns
−0.3
V
−0.3
V
−0.3
V
−0.3
V
I
SOURCE
N/A
N/A
4.0 A
1.0 mA
1.0 mA
1.0 mA
1.0 mA
I
SINK
4.0 A
100 mA
10 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
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NCV51411
PACKAGE PIN DESCRIPTION
SO−8
1
2
3
SO−16
15
16
1
DFN−18
1
2, 3, 4
5, 6, 7
PIN SYMBOL
BOOST
V
IN
V
SW
FUNCTION
The BOOST pin provides additional drive voltage to the on−chip NPN power transist-
or. The resulting decrease in switch on voltage increases efficiency.
This pin is the main power input to the IC.
This is the connection to the emitter of the on−chip NPN power transistor and serves
as the switch output to the inductor. This pin may be subjected to negative voltages
during switch off−time. A catch diode is required to clamp the pin voltage in normal
operation. This node can stand
−1.0
V for less than 50 ns during switch node flyback.
Shutdown_bar input. This is an active−low logical input, TTL compatible, with an in-
ternal pull−up current source. The IC goes into sleep mode, drawing less than 85
mA
when the pin voltage is pulled below 1.0 V. This pin may be left floating in applications
where a shutdown function is not required.
This pin provides the synchronization input.
Power return connection for the IC.
The FB pin provides input to the inverting input of the error amplifier. If V
FB
is lower
than 0.29 V, the oscillator frequency is divided by four, and current limit folds back to
about 1 ampere. These features protect the IC under severe overcurrent or short cir-
cuit conditions.
The V
C
pin provides a connection point to the output of the error amplifier and input to
the PWM comparator. Driving of this pin should be avoided because on−chip test
circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC.
No Connection
4
2
8
SHDNB
5
6
7
7
8
9
10
13
16
SYNC
GND
V
FB
8
10
17
V
C
−
3
−
6,
11
−
14
9, 11, 12,
14, 15, 18
NC
PIN CONNECTIONS
1
16
V
IN
BOOST
NC
NC
NC
NC
V
C
V
FB
BOOST
V
IN
V
SW
SHDNB
1
8
V
C
V
FB
GND
SYNC
SO−8
V
SW
SHDNB
NC
NC
NC
NC
SYNC
GND
SO−16W EP
BOOST
V
IN
V
IN
V
IN
Vsw
V
SW
V
SW
SHDNB
NC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
NC
V
C
V
FB
NC
NC
GND
NC
NC
SYNC
18−Lead DFN
Note: DFN exposed pad may be soldered to a
heat spreader for enhanced thermal perform-
ance. The exposed pad may be connected to
GND; do not connect to any other potential.
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NCV51411
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 125°C, 4.5 V< V
IN
< 40 V; unless otherwise specified.)
Characteristic
Oscillator
Operating Frequency
Frequency Line Regulation
Maximum Duty Cycle
V
FB
Frequency Foldback Threshold
PWM Comparator
Slope Compensation Voltage
Minimum Output Pulse Width
Power Switch
Current Limit
Foldback Current
Saturation Voltage
Current Limit Delay
Error Amplifier
Internal Reference Voltage
Reference PSRR
FB Input Bias Current
Output Source Current
Output Sink Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth
Open Loop Amplifier Gain
Amplifier Transconductance
Sync
Sync Frequency Range
Sync Pin Bias Current
Sync Threshold Voltage
Shutdown
Shutdown Threshold Voltage
Shutdown Pin Bias Current
Thermal Shutdown
Overtemperature Trip Point
Thermal Shutdown Hysteresis
Note 4
Note 4
175
−
185
42
195
−
°C
°C
I
CC
= 2 mA
V
SHDNB
= 0 V
1.0
0.14
1.3
5.00
1.6
35
V
mA
V
SYNC
= 0 V
V
SYNC
= 5.0 V
−
−
305
−
230
0.9
−
0.1
360
1.5
470
0.2
485
1.9
kHz
mA
mA
V
Note 4
−
V
C
= 1.270 V, V
FB
= 1.0 V
V
C
= 1.270 V, V
FB
= 2.0 V
V
FB
= 1.0 V
V
FB
= 2.0 V
Note 4
Note 4
Note 4
−
1.244
−
−
15
15
1.39
5.0
−
−
−
1.270
40
0.02
25
25
1.46
20
500
70
6.4
1.296
−
0.1
35
35
1.53
60
−
−
−
V
dB
mA
mA
mA
V
mV
kHz
dB
mA/V
V
FB
> 0.36 V
V
FB
< 0.29 V
I
OUT
= 1.5 A, V
BOOST
= V
IN
+ 2.5 V
Note 4
1.6
0.9
0.4
−
2.3
1.5
0.7
120
3.0
2.1
1.0
160
A
A
V
ns
Fix V
FB,
DV
C
/DT
ON
V
FB
to V
SW
8.0
−
17
150
26
300
mV/ms
ns
−
−
−
−
224
−
85
0.29
260
0.05
90
0.32
296
0.15
95
0.36
kHz
%/V
%
V
Test Conditions
Min
Typ
Max
Unit
4. Guaranteed by design, not 100% tested in production.
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NCV51411
ELECTRICAL CHARACTERISTICS (continued)
(−40°C < T
J
< 125°C, 4.5 V< V
IN
< 40 V; unless otherwise specified.)
Characteristic
General
Quiescent Current
Shutdown Quiescent Current
Boost Operating Current
Minimum Boost Voltage
Startup Voltage
Minimum Output Current
5. Guaranteed by design, not 100% tested in production.
I
SW
= 0 A
V
SHDNB
= 0 V
V
BOOST
−
V
SW
= 2.5 V
Note 5
−
−
−
−
6.0
−
2.2
−
4.0
20
15
−
3.3
7.0
6.25
85
40
2.5
4.4
12
mA
mA
mA/A
V
V
mA
Test Conditions
Min
Typ
Max
Unit
SHDNB
V
IN
5.0
mA
2.9 V LDO
Voltage
Regulator
Shutdown
Comparator
+
−
+
1.3 V
−
SYNC
Artificial
Ramp
Oscillator
Thermal
Shutdown
BOOST
S
R
Q
Output
Driver
V
SW
∑
+
−
1.46 V
PWM Com-
parator
−
V
FB
+
−
−
+
1.27 V
Error
Amplifier
+
0.32 V
−
+
Frequency
and Current
Limit Foldback
I
FOLDBACK
Current
Limit Com-
parator
I
REF
+
−
GND
V
C
Figure 2. Block Diagram
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