S34ML01G2
S34ML02G2
S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC
NAND Flash Memory for Embedded
Distinctive Characteristics
■
Density
❐
1 Gb / 2 Gb / 4 Gb
Architecture
❐
Input / Output Bus Width: 8 bits / 16 bits
❐
Page size:
• ×8:
1 Gb: (2048 + 64) bytes; 64-byte spare area
2 Gb / 4 Gb: (2048 + 128) bytes; 128-byte spare area
• ×16:
1 Gb: (1024 + 32) words; 32-word spare area
2 Gb / 4 Gb (1024 + 64) words; 64-word spare area
❐
Block size: 64 Pages
• ×8:
1 Gb: 128 KB+ 4 KB
2 Gb / 4 Gb: 128 KB + 8 KB
• ×16
1 Gb: 64k + 2k words
2 Gb / 4 Gb: 64k + 4k words
❐
Plane size
• ×8
1 Gb: 1024 blocks per plane or (128 MB + 4 MB
2 Gb: 1024 blocks per plane or (128 MB + 8 MB
4 Gb: 2048 blocks per plane or (256 MB + 16 MB
• ×16
1 Gb: 1024 blocks per plane or (64M + 2M) words
2 Gb: 1024 Blocks per Plane or (64M + 4M) words
4 Gb: 2048 Blocks per Plane or (128M + 8M) words
❐
■
Device Size
• 1 Gb: 1 plane per device or 128 Mbyte
• 2 Gb: 2 planes per device or 256 Mbyte
• 4 Gb: 2 planes per device or 512 Mbyte
■
NAND Flash interface
❐
Open NAND Flash Interface (ONFI) 1.0 compliant
❐
Address, Data, and Commands multiplexed
Supply Voltage
❐
3.3-V device: V
CC
= 2.7 V ~ 3.6 V
Security
❐
One Time Programmable (OTP) area
❐
Serial number (unique ID) (Contact factory for support)
❐
Hardware program/erase disabled during power transition
Additional features
❐
2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
❐
Supports Copy Back Program
❐
2 Gb and 4 Gb parts support Multiplane Copy Back Program
❐
Supports Read Cache
Electronic signature
❐
Manufacturer ID: 01h
Operating temperature
❐
Industrial: –40 °C to 85 °C
❐
Industrial Plus: –40 °C to 105 °C
■
■
■
■
■
Performance
■
Page Read / Program
❐
Random access: 25 µs (Max)
(S34ML01G2)
❐
Random access: 30 µs (Max)
(S34ML02G2, S34ML04G2)
❐
Sequential access: 25 ns (Min)
❐
Program time / Multiplane Program time: 300 µs (Typ)
Block Erase (S34ML01G2)
❐
Block Erase time: 3 ms (Typ)
Block Erase / Multiplane Erase (S34ML02G2, S34ML04G2)
❐
Block Erase time: 3.5 ms (Typ)
Reliability
❐
100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes (×8) or 264 words (×16))
❐
■
10 Year Data retention (Typ)
❐
For one plane structure (1-Gb density)
• Block zero is valid and will be valid for at least 1,000 pro-
gram-erase cycles with ECC
❐
For two plane structures (2-Gb and 4-Gb densities)
• Blocks zero and one are valid and will be valid for at least
1,000 program-erase cycles with ECC
■
■
■
Package options
❐
Pb-free and low halogen
❐
48-Pin TSOP 12 × 20 × 1.2 mm
❐
63-Ball BGA 9 × 11 × 1 mm
❐
67-Ball BGA 8 × 6.5 × 1 mm
(S34ML01G2, S34ML02G2)
Cypress Semiconductor Corporation
Document Number: 002-00499 Rev. *Q
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 13, 2018
S34ML01G2
S34ML02G2
S34ML04G2
Contents
1.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.
2.1
2.2
2.3
2.4
2.5
2.6
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
4.
4.1
4.2
4.3
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
General Description.....................................................
4
Logic Diagram................................................................ 5
Connection Diagram ...................................................... 6
Pin Description............................................................... 8
Block Diagram................................................................ 9
Array Organization ......................................................... 9
Addressing ................................................................... 11
Mode Selection ............................................................ 14
Bus Operation
............................................................
Command Input ...........................................................
Address Input...............................................................
Data Input ....................................................................
Data Output..................................................................
Write Protect ................................................................
Standby........................................................................
Command Set.............................................................
Page Read ...................................................................
Page Program..............................................................
Multiplane Program —
S34ML02G2 and S34ML04G2.....................................
Page Reprogram..........................................................
Block Erase..................................................................
Multiplane Block Erase —
S34ML02G2 and S34ML04G2.....................................
Copy Back Program.....................................................
Read Status Register...................................................
Read Status Enhanced —
S34ML02G2 and S34ML04G2.....................................
Read Status Register Field Definition ..........................
Reset............................................................................
Read Cache .................................................................
Cache Program............................................................
Multiplane Cache Program —
S34ML02G2 and S34ML04G2.....................................
Read ID........................................................................
Read ID2......................................................................
Read ONFI Signature ..................................................
Read Parameter Page .................................................
Read Unique ID (Contact Factory)...............................
One-Time Programmable (OTP) Entry ........................
Signal Descriptions
...................................................
Data Protection and Power On / Off Sequence ...........
Ready/Busy..................................................................
Write Protect Operation ...............................................
Electrical Characteristics
..........................................
Valid Blocks .................................................................
Absolute Maximum Ratings .........................................
Recommended Operating Conditions..........................
AC Test Conditions ......................................................
AC Characteristics .......................................................
DC Characteristics .......................................................
Pin Capacitance...........................................................
Thermal Resistance .....................................................
15
15
15
15
15
15
15
16
17
17
18
18
20
20
21
22
22
22
23
23
24
25
26
28
28
29
31
32
33
33
33
34
35
35
35
35
35
36
37
38
38
5.9
6.
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
6.32
7.
7.1
8.
9.
9.1
9.2
10.
Program / Erase Characteristics ................................... 38
Timing Diagrams.........................................................
39
Command Latch Cycle.................................................. 39
Address Latch Cycle ..................................................... 39
Data Input Cycle Timing................................................ 40
Data Output Cycle Timing
(CLE=L, WE#=H, ALE=L, WP#=H)............................... 40
Data Output Cycle Timing
(EDO Type, CLE=L, WE#=H, ALE=L) .......................... 41
Page Read Operation ................................................... 41
Page Read Operation
(Interrupted by CE#) ..................................................... 42
Page Read Operation Timing
with CE# Don’t Care ..................................................... 42
Page Program Operation .............................................. 43
Page Program Operation Timing
with CE# Don’t Care ..................................................... 43
Page Program Operation
with Random Data Input ............................................... 44
Random Data Output In a Page ................................... 44
Multiplane Page Program Operation —
S34ML02G2 and S34ML04G2 ..................................... 45
Block Erase Operation .................................................. 46
Multiplane Block Erase —
S34ML02G2 and S34ML04G2 ..................................... 46
Copy Back Read with Optional Data Readout .............. 47
Copy Back Program Operation
With Random Data Input............................................... 47
Multiplane Copy Back Program —
S34ML02G2 and S34ML04G2 ..................................... 48
Read Status Register Timing ........................................ 49
Read Status Enhanced Timing ..................................... 49
Reset Operation Timing ................................................ 49
Read Cache .................................................................. 50
Cache Program............................................................. 52
Multiplane Cache Program —
S34ML02G2 and S34ML04G2 ..................................... 53
Read ID Operation Timing ............................................ 55
Read ID2 Operation Timing .......................................... 55
Read ONFI Signature Timing........................................ 56
Read Parameter Page Timing ...................................... 56
Read Unique ID Timing (Contact Factory).................... 56
OTP Entry Timing ......................................................... 57
Power On and Data Protection Timing ......................... 57
WP# Handling............................................................... 57
Physical Interface
....................................................... 58
Physical Diagram .......................................................... 58
System Interface
......................................................... 61
Error Management
...................................................... 62
System Bad Block Replacement................................... 62
Bad Block Management................................................ 63
Ordering Information
.................................................. 64
Document Number: 002-00499 Rev. *Q
Page 2 of 71
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History
...................................................... 65
Sales, Solutions, and Legal Information ...........................71
Worldwide Sales and Design Support ........................... 71
Products ........................................................................ 71
PSoC® Solutions .......................................................... 71
Cypress Developer Community ..................................... 71
Technical Support ......................................................... 71
Document Number: 002-00499 Rev. *Q
Page 3 of 71
S34ML01G2
S34ML02G2
S34ML04G2
1. General Description
The S34ML01G2, S34ML02G2, and S34ML04G2 series is offered with a 3.3-V VCC power supply, and with x8 or x16 I/O interface.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks
that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is (2048 +
spare) bytes; for x16 (1024 + spare) words.
To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2 KB (
×
8) or 1 kword (
×
16) in 300 µs and an erase
operation can typically be performed in 3 ms (S34ML01G2) on a 128-kB block (
×
8) or 64k-word block (
×
16). In addition, thanks to
multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per
plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram
re-programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the
second plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during
re-program operations.
The devices are available in the TSOP48 (12 x 20 mm) package and come with the following security features:
OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently.
Serial number (unique identifier), which allows the devices to be uniquely identified. Contact factory for support of this feature.
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the datasheet. For
more details about them, contact your nearest sales office.
Document Number: 002-00499 Rev. *Q
Page 4 of 71
S34ML01G2
S34ML02G2
S34ML04G2
Table 1. Product List
Device
S34ML01G2
S34ML02G2
S34ML04G2
Density (bits)
Main
128M x 8
64M x 16
256M x 8
128M x 16
512M x 8
256M x 16
Spare
4M x 8
2M x 16
16M x 8
8M x 16
32M x 8
16M x 16
Number of Planes
1
2
2
Number of Blocks
per Plane
1024
1024
2048
1.1
Logic Diagram
Figure 1. Logic Diagram
VCC
CE#
WE#
RE#
ALE
CLE
WP#
I/O0~I/O7
R/B#
VSS
Table 2. Signal Names
Signal
I/O7 - I/O0
(×8)
I/O8 - I/O15
(×16)
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
VCC
VSS
NC
Description
Data Input / Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Read/Busy
Power Supply
Ground
Not Connected
Document Number: 002-00499 Rev. *Q
Page 5 of 71
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