PCA9554B; PCA9554C
Low-voltage 8-bit I
2
C-bus and SMBus low power I/O port with
interrupt, weak pull-up
Rev. 2 — 4 August 2015
Product data sheet
1. General description
The PCA9554B and PCA9554C are low-voltage 8-bit General Purpose Input/Output
(GPIO) expanders with interrupt and weak pull-up resistors for I
2
C-bus/SMBus
applications. The only difference between the PCA9554B and PCA9554C is their I
2
C fixed
address allowing a larger number of the same device on the I
2
C-bus with no chance of
address conflict. NXP I/O expanders provide a simple solution when additional I/Os are
needed while keeping interconnections to a minimum, for example, in ACPI power
switches, sensors, push buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide V
DD
range of 1.65 V to 5.5 V allow
the PCA9554B/PCA9554C to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9554B/PCA9554C contain a register set of 8-bit Configuration, Input, Output,
and Polarity Inversion registers.
The PCA9554B is a pin-to-pin replacement for the PCA9554, while the PCA9554C
replaces the PCA9554A. Both of these devices replace other industry-standard part
numbers. More fully-featured parts PCAL9554B and PCAL9554C are also available with
Agile I/O features. See the respective data sheet for more details.
The PCA9554B/PCA9554C open-drain interrupt (INT) output is activated when any input
state differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C-bus. Thus, the
PCA9554B/PCA9554C can remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
All input/output pins have weak pull-up resistors connected to them to eliminate external
components.
Three hardware pins (A0, A1, A2) select the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The PCA9554B and PCA9554C differ only in
their base I
2
C-bus addresses permitting a total of 16 devices on the I
2
C-bus, minimizing
the chance for address conflict, even in the most complex system.
NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
2. Features and benefits
I
2
C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5
A
(typical at 5 V V
DD
)
1.0
A
(typical at 3.3 V V
DD
)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
V
hys
= 0.10
V
DD
(typical)
5 V tolerant I/Os
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I
2
C-bus
Input/output configuration register
Polarity inversion register
Internal power-on reset
Power-up with all channels configured as inputs with weak pull-up resistors
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP16 and HVQFN16
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 4 August 2015
2 of 36
NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
3. Ordering information
Table 1.
Ordering information
Topside
mark
P4B
PA9554B
P4C
PA9554C
Package
Name
HVQFN16
TSSOP16
HVQFN16
TSSOP16
Description
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3
3
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3
3
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT758-1
SOT403-1
SOT758-1
SOT403-1
Type number
PCA9554BBS
PCA9554BPW
PCA9554CBS
PCA9554CPW
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9554BBSHP
PCA9554BPWJ
PCA9554CBSHP
PCA9554CPWJ
Package
HVQFN16
TSSOP16
HVQFN16
TSSOP16
Packing method
Reel pack, SMD,
13-inch, Turned
Reel pack, SMD,
13-inch
Reel pack, SMD,
13-inch, Turned
Reel pack, SMD,
13-inch
Minimum
order quantity
6000
2500
6000
2500
Temperature range
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA9554BBS
PCA9554BPW
PCA9554CBS
PCA9554CPW
4. Block diagram
A0
A1
A2
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
8-bit
INPUT/
OUTPUT
PORTS
write pulse
read pulse
P0
P1
P2
P3
P4
P5
P6
P7
V
DD
V
DD
POWER-ON
RESET
V
SS
PCA9554B
PCA9554C
LP
FILTER
002aah117
INT
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9554B; PCA9554C
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 4 August 2015
3 of 36
NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
5. Pinning information
5.1 Pinning
terminal 1
index area
13 SDA
12 SCL
11 INT
10 P7
9
5
6
7
8
P6
P5
14 V
DD
P4
16 A1
1
2
3
4
P3
A0
A1
A2
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aah119
16 V
DD
15 SDA
14 SCL
13 INT
12 P7
11 P6
10 P5
9
P4
A2
P0
P1
P2
PCA9554BBS
PCA9554CBS
PCA9554BPW
PCA9554CPW
V
SS
15 A0
002aah120
Transparent top view
Fig 2.
Pin configuration for TSSOP16
Fig 3.
Pin configuration for HVQFN16
5.2 Pin description
Table 3.
Symbol
A0
A1
A2
P0
[1]
P1
[1]
P2
[1]
P3
[1]
V
SS
P4
[1]
P5
[1]
P6
[1]
P7
[1]
INT
SCL
SDA
V
DD
[1]
[2]
Pin description
Pin
TSSOP16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HVQFN16
15
16
1
2
3
4
5
6
[2]
7
8
9
10
11
12
13
14
address input 0
address input 1
address input 2
Port P input/output 0
Port P input/output 1
Port P input/output 2
Port P input/output 3
supply ground
Port P input/output 4
Port P input/output 5
Port P input/output 6
Port P input/output 7
interrupt output (open-drain)
serial clock line
serial data line
supply voltage
Description
All I/O are configured as input at power-on.
HVQFN16 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
PCA9554B_PCA9554C
Product data sheet
Rev. 2 — 4 August 2015
4 of 36
NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
6. Functional description
Refer to
Figure 1 “Block diagram of PCA9554B; PCA9554C”.
6.1 Device address
slave address
0
1
0
0
A2
A1
A0 R/W
0
1
slave address
1
1
A2
A1
A0 R/W
fixed
hardware
selectable
002aah121
fixed
hardware
selectable
002aah122
a. PCA9554B address
Fig 4.
Device address
b. PCA9554C address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9554B/PCA9554C. The
lower two bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 5.
Table 4.
B7
0
0
0
0
[1]
Pointer register bits
Command byte
Pointer register bits
B5
0
0
0
0
B4
0
0
0
0
B3
0
0
0
0
B2
0
0
0
0
B1
0
0
1
1
B0
0
1
0
1
Command byte Register
(hexadecimal)
00h
01h
02h
03h
Input port
Output port
Polarity Inversion
Configuration
Protocol
read byte
read/write byte
read/write byte
read/write byte
Power-up
default
xxxx xxxx
[1]
1111 1111
0000 0000
1111 1111
B6
0
0
0
0
Undefined.
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 4 August 2015
5 of 36
Sensor
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