841S02CGILFT datasheet, PDF - EEWORLD Datasheet

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841S02CGILFT: DescriptionClock Generators & Support Products PCI Express Clock Generator; CategoryThe embedded processor and controller Microcontrollers and processors; File Size266KB，17 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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841S02CGILFT Overview

Clock Generators & Support Products PCI Express Clock Generator

841S02CGILFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP20,.25
Contacts	20
Manufacturer packaging code	PGG20
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	TSSOP 4.4 MM 0.65MM PITCH
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	6.5 mm
Humidity sensitivity level	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	100 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Master clock/crystal nominal frequency	25 MHz
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum slew rate	80 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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PCI ExpressTM Clock Generator

841S02

DATA SHEET

General Description

The 841S02 is a PLL-based clock generator specifically designed for

PCI_Express™ Clock Generation applications. This device

generates a 100MHz HCSL clock. The device offers a HCSL (Host

Clock Signal Level) clock output from a clock input reference of

25MHz. The input reference may be derived from an external source

or by the addition of a 25MHz crystal to the on-chip crystal oscillator.

An external reference may be applied to the XTAL_IN pin with the

XTAL_OUT pin left floating.

The device offers spread spectrum clock output for reduced EMI

applications. An I

C bus interface is used to enable or disable spread

spectrum operation as well as select either a down spread value of

-0.35% or -0.5%.

Features

•

Two 0.7V current mode differential HCSL output pairs

Crystal oscillator interface: 25MHz

Output frequency: 100MHz

RMS period jitter: 3ps (maximum)

Output skew: 35ps (maximum)

Cycle-to-cycle jitter: 35ps (maximum)

C support with readback capabilities up to 400kHz

Spread Spectrum for electromagnetic interference (EMI) reduction

3.3V operating supply mode

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

Block Diagram

25MHz

Pin Assignment

XTAL_IN

OSC

XTAL_OUT

SDATA

Pullup

SCLK

Pullup

PLL

Divider

Network

SRCT[1:2]

SRCC[1:2]

Logic

SRCT2

SRCC2

SRCT1

SRCC1

IREF

SDATA

SCLK

XTAL_OUT

XTAL_IN

DDA

IREF

841S02

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm package body

G Package

Top View

841S02 Rev A 11/16/15

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