Features
•
•
•
•
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Pages (264 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Memory Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
5.0V-tolerant Inputs: SI, SCK, CS, RESET, and WP Pins
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free/RoHS Compliant) Package Options
•
•
•
•
•
•
•
•
4-megabit
2.5-volt or
2.7-volt
DataFlash
®
AT45DB041B
1. Description
The AT45DB041B is an SPI compatible serial interface Flash memory ideally suited
for a wide variety of digital voice-, image-, program code- and data-storage applica-
tions. Its 4,325,376 bits of memory are organized as 2048 pages of 264 bytes each. In
addition to the main memory, the AT45DB041B also contains two SRAM data buffers
of 264 bytes each.
The buffers allow receiving of data while a page in the main memory is being repro-
grammed, as well as reading or writing a continuous data stream. EEPROM emulation
(bit or byte alterability) is easily handled with a self-contained three step Read-Modify-
Write operation. Unlike conventional Flash memories that are accessed randomly with
multiple address lines and a parallel interface, the DataFlash uses a SPI serial inter-
face to sequentially access its data. DataFlash supports SPI mode 0 and mode 3. The
simple serial interface facilitates hardware layout, increases system reliability, mini-
mizes switching noise, and reduces package size and active pin count. The device is
optimized for use in many commercial and industrial applications where high density,
low pin count, low voltage, and low power are essential. The device operates at clock
frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the AT45DB041B does not require
high input voltages for programming. The device operates from a single power supply,
2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The
AT45DB041B is enabled through the chip select pin (CS) and accessed via a three-
wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
3443D–DFLSH–2/08
For New
Designs Use
AT45DB041D
When the device is shipped from Atmel, the most significant page of the memory array may not
be erased. In other words, the contents of the last page may not be filled with FFH.
2. Pin Configurations and Packages
Table 2-1.
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Pin Configurations
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write Protect Pin
Chip Reset
Ready/Busy
Figure 2-1.
TSOP Top View Type 1
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-2.
CASON – Top View through Package
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
Figure 2-3.
SI
SCK
RESET
CS
8-SOIC
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
SO
GND
VCC
WP
Figure 2-4.
28-SOIC
(1)
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-5.
CBGA Top View
through Package
1
2
3
A
NC
NC
VCC
B
SCK
GND
C
CS RDY/BSY WP
D
SO
SI
NC
RESET
NC
E
NC
Note:
1. The next generation DataFlash devices will not be
offered in 28-SOIC package, therefore, this pack-
age is not recommended for new designs.
2
AT45DB041B
3443D–DFLSH–2/08
AT45DB041B
3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB041B is divided into three levels of
granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis; however, the optional
erase operations can be performed at the block or page level.
Figure 4-1.
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0
BLOCK 1
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
SECTOR 1 = 248 Pages
65,472 bytes (62K + 1984)
PAGE ARCHITECTURE
8 Pages
BLOCK 0
PAGE 0
PAGE 1
SECTOR 1
BLOCK 2
SECTOR 2 = 256 Pages
67,584 bytes (64K + 2K)
PAGE 6
PAGE 7
PAGE 8
BLOCK 30
BLOCK 31
SECTOR 2
SECTOR 3 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 33
BLOCK 1
BLOCK 32
PAGE 9
PAGE 14
PAGE 15
BLOCK 62
SECTOR 4 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 63
BLOCK 64
BLOCK 65
PAGE 16
PAGE 17
PAGE 18
SECTOR 5 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 254
BLOCK 255
PAGE 2045
PAGE 2046
PAGE 2047
Block = 2112 bytes
(2K + 64)
Page = 264 bytes
(256 + 8)
3
3443D–DFLSH–2/08
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with
the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling the SCK pin controls the loading of
the opcode and the desired buffer or main memory address location through the SI (serial input)
pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8 - BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA10 - PA0 and BA8 - BA0 where PA10 - PA0
denotes the 11 address bits required to designate a page address and BA8 - BA0 denotes the
nine address bits required to designate a byte address within the page.
5.1
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two data buffers. The DataFlash supports two categories of read modes in relation to
the SCK signal. The differences between the modes are in respect to the inactive state of the
SCK signal as well as which clock cycle data will begin to be output. The two categories, which
are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock
Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to
Table 5-3 on page 10
for a complete list) is used to select which category will be used for reading. Please refer to the
“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle
sequences for each mode.
5.1.1
Continuous Array Read
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be
clocked into the device followed by 24 address bits and 32 don’t care bits. The first four bits of
the 24-bit address sequence are reserved for upward and downward compatibility to larger and
smaller density devices (see Notes under “Command Sequence for Read/Write Operations” dia-
gram). The next 11 address bits (PA10 - PA0) specify which page of the main memory array to
read, and the last nine bits (BA8 - BA0) of the 24-bit address sequence specify the starting byte
address within the page. The 32 don’t care bits that follow the 24 address bits are needed to ini-
tialize the read operation. Following the 32 don’t care bits, additional clock pulses on the SCK
pin will result in serial data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a Con-
tinuous Array Read, the device will continue reading at the beginning of the next page with no
delays incurred during the page boundary crossover (the crossover from the end of one page to
the beginning of the next page). When the last bit in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with crossing
over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
4
AT45DB041B
3443D–DFLSH–2/08
AT45DB041B
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the f
CAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
5.1.2
Main Memory Page Read
A Main Memory Page Read allows the user to read data directly from any one of the 2048 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device fol-
lowed by 24 address bits and 32 don’t care bits. The first four bits of the 24-bit address
sequence are reserved bits, the next 11 address bits (PA10 - PA0) specify the page address,
and the next nine address bits (BA8 - BA0) specify the starting byte address within the page.
The 32 don’t care bits which follow the 24 address bits are sent to initialize the read operation.
Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on
the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in main mem-
ory is reached during a Main Memory Page Read, the device will continue reading at the
beginning of the same page. A low-to-high transition on the CS pin will terminate the read oper-
ation and tri-state the SO pin.
Buffer Read
Data can be read from either one of the two buffers, using different opcodes to specify which
buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode
of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the
opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t care bits. Since
the buffer size is 264 bytes, nine address bits (BFA8 - BFA0) are required to specify the first byte
of data to be read from the buffer. The CS pin must remain low during the loading of the opcode,
the address bits, the don’t care bits, and the reading of data. When the end of a buffer is
reached, the device will continue reading back at the beginning of the buffer. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the SO pin.
5.1.4
Status Register Read
The status register can be used to determine the device’s Ready/Busy status, the result of a
Main Memory Page to Buffer Compare operation, or the device density. To read the status reg-
ister, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is
shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on
the SO pin during the next eight clock cycles. The five most significant bits of the status register
will contain device information, while the remaining three least-significant bits are reserved for
future use and will have undefined values. After bit 0 of the status register has been shifted out,
the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting
again with bit 7. The data in the status register is constantly updated, so each repeating
sequence will output new data.
5.1.3
Table 5-1.
Bit 7
RDY/BUSY
Status Register Format
Bit 6
COMP
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
X
Bit 0
X
5
3443D–DFLSH–2/08
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