16-Bit, 80/100 MSPS ADC
AD9446
FEATURES
100 MSPS guaranteed sampling rate (AD9446-100)
83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS)
82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS)
89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS)
95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±3.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
3.3 V and 5 V supply operation
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2
DRGND DRVDD
DFS
DCS MODE
BUFFER
VIN+
VIN–
T/H
PIPELINE
ADC
16
CMOS
OR
LVDS
OUTPUT
STAGING
2
32
D15 TO D0
2
DCO
REF
05490-001
AD9446
OUTPUT MODE
OR
CLK+
CLK–
CLOCK
AND TIMING
MANAGEMENT
VREF SENSE REFT REFB
Figure 1.
APPLICATIONS
MRI receivers
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9446 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
True 16-bit linearity.
High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
Packaged in a Pb-free, 100-lead TQFP/EP package.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
GENERAL DESCRIPTION
The AD9446 is a 16-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
product operates up to a 100 MSPS, providing superior SNR for
instrumentation, medical imaging, and radar receivers
employing baseband (<100 MHz) IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
3.
4.
5.
6.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9446
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Terminology .......................................................................................9
Pin Configurations and Function Descriptions ......................... 10
Equivalent Circuits......................................................................... 15
Typical Performance Characteristics ........................................... 16
Theory of Operation ...................................................................... 24
Analog Input and Reference Overview ................................... 24
Clock Input Considerations...................................................... 26
Power Considerations................................................................ 27
Digital Outputs ........................................................................... 27
Timing ......................................................................................... 27
Operational Mode Selection ..................................................... 28
Evaluation Board ............................................................................ 29
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD9446
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), A
IN
= −1.0 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
1
Integral Nonlinearity (INL)
1
VOLTAGE REFERENCE
Output Voltage
1
VREF = 1.6 V (3.2 V p-p Analog Input Range)
Load Regulation @ 1.0 mA
Reference Input Current (External 1.6 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
VREF = 1.6 V
VREF = 1.0 V (External)
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance
2
Input Capacitance
2
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
I
AVDD1
I
AVDD21
I
DRVDD1
—LVDS Outputs
I
DRVDD1
—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
LVDS Outputs
CMOS Outputs (DC Input)
1
Temp
Full
Full
Full
Full
25°C
Full
25°C
AD9446BSVZ-80
Min
Typ
Max
16
Guaranteed
−5
±0.1
+5
−3
±0.6
+3
−2
±0.3
+2
−0.75 ±0.4
+0.75
−5
±3.0
+5
AD9446BSVZ-100
Min
Typ
Max
16
Guaranteed
−5
±0.1
+5
−3
±0.5
+3
−2
±0.3
+2
−0.85 ±0.4
+0.85
−6
±3.0
+6
Unit
Bits
mV
% FSR
% FSR
LSB
LSB
Full
Full
Full
25°C
1.6
±2
1.5
1.6
±2
1.9
V
mV
μA
LSB rms
Full
Full
Full
Full
Full
Full
3.2
2.0
3.5
3.2
1
6
3.8
3.2
3.2
2.0
3.5
3.8
1
6
V p-p
V p-p
V
V
kΩ
pF
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
3.14
4.75
3.0
3.0
3.3
5.0
3.3
3.3
335
204
68
14
1
0.2
2.4
2.2
3.46
5.25
3.6
3.6
365
234
75
3.14
4.75
3.0
3.0
3.3
5.0
3.3
3.3
368
223
69
14
1
0.2
3.46
5.25
3.6
3.6
401
255
75
V
V
V
V
mA
mA
mA
mA
mV/V
%/V
2.6
2.6
2.3
2.8
W
W
Measured at the maximum clock rate, f
IN
= 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
Rev. 0 | Page 3 of 36
AD9446
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), A
IN
= −1 dBFS, DCS on, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 10 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 92 MHz
f
IN
= 125 MHz
f
IN
= 170 MHz
f
IN
= 10 MHz (2 V p-p Input)
f
IN
= 30 MHz (2 V p-p Input)
f
IN
= 70 MHz (2 V p-p Input)
f
IN
= 92 MHz (2 V p-p Input)
f
IN
= 125 MHz (2 V p-p Input)
f
IN
= 170 MHz (2 V p-p Input)
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 10 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 92 MHz
f
IN
= 125 MHz
f
IN
= 170 MHz
f
IN
= 10 MHz (2 V p-p Input)
f
IN
= 30 MHz (2 V p-p Input)
f
IN
= 70 MHz (2 V p-p Input)
f
IN
= 92 MHz (2 V p-p Input)
f
IN
= 125 MHz (2 V p-p Input)
f
IN
= 170 MHz (2 V p-p Input)
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 10 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 92 MHz
f
IN
= 125 MHz
f
IN
= 170 MHz
Temp
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
77.1
75.9
74.9
75.5
74.4
AD9446BSVZ-80
Min
Typ
Max
79.6
80.5
79.2
79.0
78.2
81.8
81.6
80.6
80.1
78.8
77.1
78.3
78.3
77.6
77.5
76.7
75.5
80.5
80.4
78.6
79.2
74.9
66.0
77.9
77.8
77.1
77.1
75.7
72.5
13.2
13.2
12.9
13.0
12.3
10.8
76.9
75.5
71.7
73.8
69.1
AD9446BSVZ-100
Min
Typ
Max
78.4
78.3
77.9
77.7
77.6
79.7
79.5
79.0
78.9
78.2
77.0
76.6
76.6
76.2
76
75.6
75.1
78.9
78.6
77.7
77.1
76.9
70.5
76.2
76.1
75.9
75.7
75.3
73.6
13.0
12.9
12.8
12.7
12.6
11.6
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
Bits
Rev. 0 | Page 4 of 36
AD9446
Parameter
SPURIOUS-FREE DYNAMIC RANGE
(SFDR, Second or Third Harmonic)
f
IN
= 10 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 92 MHz
f
IN
= 125 MHz
f
IN
= 170 MHz
f
IN
= 10 MHz (2 V p-p Input)
f
IN
= 30 MHz (2 V p-p Input)
f
IN
= 70 MHz (2 V p-p Input)
f
IN
= 92 MHz (2 V p-p Input)
f
IN
= 125 MHz (2 V p-p Input)
f
IN
= 170 MHz (2 V p-p Input)
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS
f
IN
= 10 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 92 MHz
f
IN
= 125 MHz
f
IN
= 170 MHz
f
IN
= 10 MHz (2 V p-p Input)
f
IN
= 30 MHz (2 V p-p Input)
f
IN
= 70 MHz (2 V p-p Input)
f
IN
= 92 MHz (2 V p-p Input)
f
IN
= 125 MHz (2 V p-p Input)
f
IN
= 170 MHz (2 V p-p Input)
TWO-TONE SFDR
f
IN
= 10.8 MHz @ −7 dBFS,
9.8 MHz @ −7 dBFS
f
IN
= 70.3 MHz @ −7 dBFS,
69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
Temp
AD9446BSVZ-80
Min
Typ
Max
AD9446BSVZ-100
Min
Typ
Max
Unit
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
82
82
80
80
79
90
89
87
84
80
66
92
93
92
90
85
77
82
82
79
81
77
92
89
89
84
83
74
94
92
92
89
87
82
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
−98
−97
−98
−98
−96
−95
−97
−97
−94
−97
−97
−93
−89
−89
−89
−90
−89
−96
−97
−96
−95
−96
−92
−93
−96
−94
−99
−95
−95
−91
−89
−87
−90
−88
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
96
92
325
95
92
540
dBFS
dBFS
MHz
Rev. 0 | Page 5 of 36
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