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SY10EP32VZGTR

Description
100EP SERIES, PRESCALER, PDSO8
Categorylogic    logic   
File Size121KB,9 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Parametric View All

SY10EP32VZGTR Overview

100EP SERIES, PRESCALER, PDSO8

SY10EP32VZGTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
Parts packaging codeSOIC
package instructionSOP,
Contacts8
Reach Compliance Codecompliant
Other featuresALSO OPERATES AT 5V SUPPLY; PECL MODE: VEE =0V WITH VCC =3.3V TO 5V
series10EP
JESD-30 codeR-PDSO-G8
JESD-609 codee4
length4.93 mm
Logic integrated circuit typePRESCALER
Humidity sensitivity level1
Number of data/clock inputs1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
propagation delay (tpd)0.43 ns
Certification statusNot Qualified
Maximum seat height1.73 mm
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.94 mm
minfmax4000 MHz
Micrel, Inc.
5V/3.3V
÷
2 DIVIDER
Precision Edge®
Precision
SY10EP32V
Edge
®
SY100EP32V
SY10EP32V
SY100EP32V
FEATURES
Guaranteed maximum frequency > 4GHz
3.3V and 5V power supply options
Guaranteed propagation delay <440ps over
temperature
Internal 75K
input pull-down resistors
Wide operating temperature range: –40
°
C to +85
°
C
Available in 8-pin MSOP and SOIC packages
ECL Pro™
DESCRIPTION
The SY10/100EP32V is an integrated
÷2
divider with
differential clock inputs.
The V
BB
pin, an internally generated voltage supply,
is available to this device only. For single-ended input
conditions, the unused differential input is connected to
V
BB
as a switching reference voltage. V
BB
may also rebias
AC-coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01µF capacitor and limit current sourcing or sinking
to 0.5mA. When not used, V
BB
should be left open.
The reset pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the reset allows for the
synchronous use of multiple EP32’s in a system.
The 100k series includes internal temperature
compensation circuitry.
PIN NAMES
Pin
CLK, /CLK
Reset
V
BB
Q, /Q
Function
ECL Clock Inputs
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
TRUTH TABLE
(1)
CLK
X
Z
Note 1:
/CLK
X
/Z
RESET
Z
L
Q
L
F
/Q
H
F
Z = LOW-to-HIGH Transition
/Z = HIGH-to-LOW Transition
F = Divide by 2 function.
ECL Pro is a trademarks of Micrel, Inc.
Precision Edge is a registered trademarks of Micrel, Inc.
M9999-111605
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: September 2005
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