E2U0041-28-81
¡ Semiconductor
MSM7717-01/02/03
¡ Semiconductor
Single Rail CODEC
This version: Aug. 1998
MSM7717-01/02/03
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals and telephone terminals in digital wireless systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver
differentially.
FEATURES
• Single power supply: 2.7 V to 3.8 V
• Low power consumption
Operating mode:
20 mW Typ. V
DD
= 3 V
Power-down mode:
0.03 mW Typ. V
DD
= 3 V
• Conforms to ITU-T Companding law
MSM7717-01:
m/A-law
pin selectable
MSM7717-02:
m-law
MSM7717-03: A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024 kHz
96/192/384/768/1536/1544/2048/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name: MSM7717-01GS-K)
(Product name: MSM7717-02GS-K)
(Product name: MSM7717-03GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)
(Product name: MSM7717-02MS-K)
(Product name: MSM7717-03MS-K)
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¡ Semiconductor
MSM7717-01/02/03
BLOCK DIAGRAM
AIN–
AIN+
GSX
–
+
RC
LPF
8th
BPF
AD
CONV.
AUTO
ZERO
PCMOUT
TCONT
PLL
XSYNC
BCLK
SGC
SG
SG
GEN
VR
GEN
RTIM
RSYNC
(ALAW)
VFRO
PWI
AOUT–
–
+
SG
5th
LPF
DA
CONV.
RCONT
PCMIN
–
+
–
+
SG
PWD
PWD
Logic
AOUT+
SG
PDN
V
DD
AG
DG
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¡ Semiconductor
MSM7717-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG 1
AOUT+ 2
AOUT– 3
NC 4
PWI 5
VFRO 6
NC 7
V
DD
8
DG 9
PDN 10
RSYNC 11
PCMIN 12
24 SGC
SG 1
20 SGC
23 AIN+
22 AIN–
21 GSX
20 NC
AOUT+ 2
AOUT– 3
PWI 4
19 AIN+
18 AIN–
17 GSX
16 NC
VFRO 5
V
DD
6
DG 7
19 NC
15 (ALAW)*
14 AG
18 (ALAW)*
17 NC
PDN 8
13 BCLK
16 AG
RSYNC 9
12 XSYNC
15 BCLK
PCMIN 10
11 PCMOUT
14 XSYNC
13 PCMOUT
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K.
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¡ Semiconductor
MSM7717-01/02/03
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed in any method shown below. When not using AIN–
and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down
modes, the GSX output is at AG voltage.
1) Inverting input type
C1
Analog input
R1
GSX
AIN–
AIN+
SG
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1) (F)
Gain = R2/R1
<
10
R2
–
+
2) Noninverting input type
C2
Analog input
R5
R4
R3
AIN+
AIN–
GSX
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2
¥
3.14
¥
30
¥
R5) (F)
Gain = 1 + R4 / R3
£
10
AG
Analog signal ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.0 V
PP
above and below the signal ground voltage (SG)
when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving mode this output is in a high impedance state, and during power-down
mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.
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¡ Semiconductor
PWI, AOUT+, AOUT–
MSM7717-01/02/03
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to
the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT–. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during
the power-down mode.
VI
R6
R7
Gain = VO/VI = R7/R6
£
1
Analog output
VO ZL
SG
–
+
AOUT+
Analog inverted output
ZL > 1.2 kW
R6 > 20 kW
External Signal Input
Receive filter
–
+
VFRO
PWI
AOUT–
SG
V
DD
Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.
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