FLLXT971ABCA4 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Topical application> Wireless rf/communication> FLLXT971ABCA4

FLLXT971ABCA4: DescriptionDATACOM, ETHERNET TRANSCEIVER, PQFP64; CategoryTopical application Wireless rf/communication; File Size561KB，90 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric Compare View All

FLLXT971ABCA4 Overview

DATACOM, ETHERNET TRANSCEIVER, PQFP64

FLLXT971ABCA4 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Rated supply voltage	3.3 V
Processing package description	LQFP-64
state	TRANSFERRED
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK
surface mount	Yes
Terminal form	GULL WING
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
Communication type	Ethernet transceiver

Preview

Download Datasheet

View All

Intel

LXT971A

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Datasheet

The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both

100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for

easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a

Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.

This document also supports the LXT971 device.

The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition

can be set using auto-negotiation, parallel detection, or manual control.

The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V

power supply.

Applications

■

Combination 10BASE-T/100BASE-TX or

100BASE-FX Network Interface Cards

(NICs)

■

10/100 PCMCIA Cards

Cable Modems and Set-Top Boxes

Product Features

■

3.3V Operation.

Low power consumption (300 mW

typical).

Low-power “Sleep” mode.

10BASE-T and 100BASE-TX using a

single RJ-45 connection.

Supports auto-negotiation and parallel

detection.

MII interface with extended register

capability.

Robust baseline wander correction

performance.

100BASE-FX fiber-optic capable.

Standard CSMA/CD or full-duplex

operation.

Supports JTAG boundary scan.

■

Configurable via MDIO serial port or

hardware control pins.

Integrated, programmable LED drivers.

64-ball Plastic Ball Grid Array (PBGA).

— LXT971ABC - Commercial (0

C ambient).

— LXT971ABE - Extended (-40

to 85

ambient).

64-pin Low-profile Quad Flat Package

(LQFP).

— LXT971ALC - Commercial (0

C ambient).

— LXT971ALE - Extended (-40

to 85

ambient).

Order Number: 249414-002

August 2002

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver

Contents

1.0

2.0

3.0

Pin Assignments ..............................................................................................................................12

Signal Descriptions ..........................................................................................................................16

Functional Description.....................................................................................................................21

3.1

Introduction .......................................................................................................................21

3.1.1

Comprehensive Functionality .............................................................................21

3.1.2

OSP™ Architecture ............................................................................................21

Network Media / Protocol Support....................................................................................22

3.2.1

10/100 Network Interface ...................................................................................22

3.2.1.1 Twisted-Pair Interface ..........................................................................22

3.2.1.2 Fiber Interface.......................................................................................22

3.2.1.3 Fault Detection and Reporting..............................................................23

3.2.2

MII Data Interface...............................................................................................23

3.2.2.1 Increased MII Drive Strength ...............................................................23

3.2.3

Configuration Management Interface .................................................................24

3.2.3.1 MDIO Management Interface ..............................................................24

3.2.3.2 Hardware Control Interface ..................................................................25

Operating Requirements....................................................................................................26

3.3.1

Power Requirements ...........................................................................................26

3.3.2

Clock Requirements............................................................................................26

3.3.2.1 External Crystal/Oscillator ...................................................................26

3.3.2.2 MDIO Clock .........................................................................................26

Initialization.......................................................................................................................26

3.4.1

MDIO Control Mode ..........................................................................................26

3.4.2

Hardware Control Mode .....................................................................................27

3.4.3

Reduced Power Modes........................................................................................28

3.4.3.1 Hardware Power Down ........................................................................28

3.4.3.2 Software Power Down..........................................................................29

3.4.3.3 Sleep Mode ...........................................................................................29

3.4.4

Reset....................................................................................................................29

3.4.5

Hardware Configuration Settings........................................................................30

Establishing Link...............................................................................................................31

3.5.1

Auto-Negotiation ................................................................................................31

3.5.1.1 Base Page Exchange .............................................................................31

3.5.1.2 Next Page Exchange .............................................................................31

3.5.1.3 Controlling Auto-Negotiation...............................................................31

3.5.2

Parallel Detection ................................................................................................31

MII Operation....................................................................................................................32

3.6.1

MII Clocks ..........................................................................................................32

3.6.2

Transmit Enable ..................................................................................................33

3.6.3

Receive Data Valid .............................................................................................33

3.6.4

Carrier Sense .......................................................................................................33

3.6.5

Error Signals .......................................................................................................33

3.6.6

Collision ..............................................................................................................33

3.6.7

Loopback.............................................................................................................34

3.6.7.1 Operational Loopback ..........................................................................35

3.2

3.3

3.4

3.5

3.6

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver

3.7

3.8

3.9

3.10

3.6.7.2 Test Loopback...................................................................................... 35

100 Mbps Operation ......................................................................................................... 36

3.7.1

100BASE-X Network Operations...................................................................... 36

3.7.2

Collision Indication ............................................................................................ 38

3.7.3

100BASE-X Protocol Sublayer Operations ....................................................... 38

3.7.3.1 PCS Sublayer ....................................................................................... 38

3.7.3.2 PMA Sublayer...................................................................................... 41

3.7.3.3 Twisted-Pair PMD Sublayer ................................................................ 42

3.7.3.4 Fiber PMD Sublayer ............................................................................ 43

10 Mbps Operation ........................................................................................................... 43

3.8.1

10BASE-T Preamble Handling.......................................................................... 43

3.8.2

10BASE-T Carrier Sense ................................................................................... 43

3.8.3

10BASE-T Dribble Bits ..................................................................................... 43

3.8.4

10BASE-T Link Integrity Test........................................................................... 44

3.8.4.1 Link Failure.......................................................................................... 44

3.8.5

10BASE-T SQE (Heartbeat) .............................................................................. 44

3.8.6

10BASE-T Jabber .............................................................................................. 44

3.8.7

10BASE-T Polarity Correction .......................................................................... 44

Monitoring Operations ..................................................................................................... 44

3.9.1

Monitoring Auto-Negotiation ............................................................................ 44

3.9.1.1 Monitoring Next Page Exchange......................................................... 45

3.9.2

LED Functions ................................................................................................... 45

3.9.2.1 LED Pulse Stretching........................................................................... 45

Boundary Scan (JTAG1149.1) Functions ........................................................................ 46

3.10.1 Boundary Scan Interface .................................................................................... 46

3.10.2 State Machine..................................................................................................... 46

3.10.3 Instruction Register ............................................................................................ 46

3.10.4 Boundary Scan Register (BSR).......................................................................... 46

Magnetics Information ..................................................................................................... 48

Typical Twisted-Pair Interface ......................................................................................... 48

The Fiber Interface ........................................................................................................... 52

Electrical Parameters ........................................................................................................ 56

Timing Diagrams .............................................................................................................. 61

4.0

Application Information.................................................................................................................. 48

4.1

4.2

4.3

5.0

Test Specifications .......................................................................................................................... 56

5.1

5.2

6.0

7.0

8.0

Register Definitions ........................................................................................................................ 71

Package Specifications.................................................................................................................... 88

Product Ordering Information......................................................................................................... 90

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver

Figures

LXT971A Block Diagram...................................................................................................9

64-Pin PBGA Pin Assignments.........................................................................................10

64-Pin LQFP Pin Assignments..........................................................................................11

Management Interface Read Frame Structure...................................................................21

Management Interface Write Frame Structure ..................................................................21

Interrupt Logic...................................................................................................................22

Initialization Sequence ......................................................................................................24

Hardware Configuration Settings ......................................................................................26

Link Establishment Overview ...........................................................................................28

10BASE-T Clocking .........................................................................................................30

100BASE-X Clocking .......................................................................................................30

Link Down Clock Transition.............................................................................................30

Loopback Paths .................................................................................................................31

100BASE-X Frame Format...............................................................................................32

100BASE-TX Data Path....................................................................................................33

100BASE-TX Reception with no Errors...........................................................................33

100BASE-TX Reception with Invalid Symbol .................................................................33

100BASE-TX Transmission with no Errors......................................................................34

100BASE-TX Transmission with Collision......................................................................34

Protocol Sublayers.............................................................................................................35

LED Pulse Stretching ........................................................................................................42

Typical Twisted-Pair Interface - Switch............................................................................45

Typical Twisted-Pair Interface - NIC................................................................................46

Typical MII Interface ........................................................................................................47

Typical Fiber Interface ......................................................................................................48

100BASE-TX Receive Timing - 4B Mode .......................................................................53

100BASE-TX Transmit Timing - 4B Mode......................................................................54

100BASE-FX Receive Timing..........................................................................................55

100BASE-FX Transmit Timing ........................................................................................56

10BASE-T Receive Timing ..............................................................................................57

10BASE-T Transmit Timing.............................................................................................58

10BASE-T Jabber and Unjabber Timing ..........................................................................59

10BASE-T SQE (Heartbeat) Timing.................................................................................59

Auto Negotiation and Fast Link Pulse Timing..................................................................60

Fast Link Pulse Timing .....................................................................................................60

MDIO Input Timing ..........................................................................................................61

MDIO Output Timing........................................................................................................61

Power-Up Timing..............................................................................................................62

RESET Pulse Width and Recovery Timing ......................................................................62

PHY Identifier Bit Mapping..............................................................................................68

PBGA Package Specification ............................................................................................79

LXT971A LQFP Package Specifications..........................................................................80

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

FLLXT971ABCA4 Related Products

	FLLXT971ABCA4	LXT971A	LXT971ABC	LXT971ABE	LXT971ALC	LXT971ALE	FLLXT971ABEA4	DJLXT971ALEA4	DJLXT971ALCA4
Description	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64	DATACOM, ETHERNET TRANSCEIVER, PQFP64
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	64	64	64	64	64	64	64	64	64
Maximum operating temperature	70 Cel	70 Cel	70 °C	85 °C	70 °C	85 °C	70 Cel	70 Cel	70 Cel
Minimum operating temperature	0.0 Cel	0.0 Cel	-	-40 °C	-	-40 °C	0.0 Cel	0.0 Cel	0.0 Cel
surface mount	Yes	Yes	YES	YES	YES	YES	Yes	Yes	Yes
Terminal form	GULL WING	GULL WING	BALL	BALL	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	Four	Four	BOTTOM	BOTTOM	QUAD	QUAD	Four	Four	Four
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Rated supply voltage	3.3 V	3.3 V	-	-	-	-	3.3 V	3.3 V	3.3 V
Processing package description	LQFP-64	LQFP-64	-	-	-	-	LQFP-64	LQFP-64	LQFP-64
state	TRANSFERRED	TRANSFERRED	-	-	-	-	TRANSFERRED	TRANSFERRED	TRANSFERRED
Craftsmanship	CMOS	CMOS	-	-	-	-	CMOS	CMOS	CMOS
packaging shape	SQUARE	SQUARE	-	-	-	-	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK	FLATPACK	-	-	-	-	FLATPACK	FLATPACK	FLATPACK
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy	-	-	-	-	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy
Communication type	Ethernet transceiver	Ethernet transceiver	-	-	-	-	Ethernet transceiver	Ethernet transceiver	Ethernet transceiver

Recommended Resources

Application of LM3886 in home theater 01

High-precision voltage stabilization circuit diagram

Automatic control circuit for temperature control and timing operation of electric heating kiln

DSX-50A type infrared high temperature electronic disinfection cabinet circuit diagram

+1.235V low power reference source

Stock market trends, bull and bear markets: [[i] 本帖最后由 lopopo 于 2009-12-8 21:41 编辑 [/i]]...; lopopo Talking

Several issues that cannot be ignored in if statements! --Teacher Li Jiakai from Wuhan Huaqian: [b]Author: Li Jiakai, Wuhan Huaqian Embedded Training Center[/b] In view of the various problems that students often encounter in programming due to ignoring if judgment statements during the teaching...; 武汉linux Embedded System

DC Transformer Simulation Problem: Dear seniors, please help me urgently: How to use Mutisim10 to model and simulate a DC transformer? It is known that the input DC current is 20MA and the output is 5V. Please see the attachment for th...; rose1974 Analog electronics

Learn MSP430F5529 programming routine 1: Use the multi-channel timing of Timer_A comparison mode to make the LED flash.MSP430 has two types of timers: Timer_A (3)Timer_B (1).Each timer is equipped with different capture compare registers: Ti...; Aguilera Microcontroller MCU

Why can't I reply to the post?: I'm a newbie, why can't I reply to other people's posts?...; alice_gjy Talking

Some engineers’ testimonials: Very true! What these experienced engineers say may give you some inspiration!...; 80后 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components