Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
F
EATURES
•
1 LVCMOS / LVTTL output
•
Differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Maximum output frequency: 350MHz (typical)
•
Part-to-part skew: 500ps (maximum)
•
Small 8 lead SOIC package saves board space
•
Full 3.3V, 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Pin-to-pin compatible with MC100EPT21
G
ENERAL
D
ESCRIPTION
T h e I C S 8 3 021I i s a 1 - t o -1 Differential-to-
LVCMOS/LVTTL Translator and a member of the
HiPerClockS™
HiPerClockS™family of High Perfor mance
Clock Solutions from ICS. The differential input
is highly flexible and can accept the following
input types: LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The
small 8-lead SOIC footprint makes this device ideal for use in
applications with limited board space.
ICS
B
LOCK
D
IAGRAM
CLK
nCLK
Q0
P
IN
A
SSIGNMENT
nc
CLK
nCLK
nc
1
2
3
4
8
7
6
5
V
DD
Q0
nc
GND
ICS83021I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
83021AMI
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 30, 2004
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
Type
Unused
Input
Input
Power
Output
Power
Pullup
Description
No connect.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Power supply ground.
Single clock output. LVCMOS / LVTTL interface levels.
Positive supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 4, 6
2
3
5
7
8
Name
nc
CLK
nCLK
GND
Q0
V
DD
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
Test Conditions
Minimum
Typical
4
V
DD
= 3.6V
23
51
51
7
12
Maximum
Units
pF
pF
KΩ
KΩ
Ω
83021AMI
www.icst.com/products/hiperclocks.html
2
REV. B JUNE 30, 2004
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V or 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
2.375
Typical
3.3
2.5
Maximum
3.6
2.625
20
Units
V
V
mA
T
ABLE
3BC. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V or 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
Parameter
Output High Voltage; NOTE 1
Test Conditions
V
DD
= 3.6V
V
DD
= 2.625V
Minimum
2.6
1.8
Typical
Maximum
Units
V
V
V
V
OL
Output Low Voltage; NOTE 1
0.5
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information, Output Load Test Circuit
Diagrams.
T
ABLE
3C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V or 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
IN
= V
DD
= 3.6V or 2.625V
V
IN
= V
DD
= 3.6V or 2.625V
V
IN
= 0V, V
DD
= 3.6V or 2.625V
V
IN
= 0V, V
DD
= 3.6V or 2.625V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
83021AMI
www.icst.com/products/hiperclocks.html
3
REV. B JUNE 30, 2004
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
Test Conditions
IJ 350MHz
0.8V to 2V
IJ 166MHz
Minimum
1.7
100
45
Typical
350
2.0
250
50
2.3
500
400
55
Maximum
Units
MHz
ns
ps
ps
%
%
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay, NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
t
sk(pp)
t
R
/ t
F
odc
166MHz < ƒ
≤
350MHz
40
50
60
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay, NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 250MHz
250
45
50
IJ 350MHz
1.9
Test Conditions
Minimum
Typical
350
2.2
2.5
500
550
55
Maximum
Units
MHz
ns
ps
ps
%
%
t
sk(pp)
t
R
/ t
F
odc
250MHz < ƒ
≤
350MHz
40
50
60
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
83021AMI
www.icst.com/products/hiperclocks.html
4
REV. B JUNE 30, 2004
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V ± 0.15V
1.25V ± 5%
V
DD
Qx
SCOPE
V
DD
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V ± 0.15V
-1.25V ± 5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
DD
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
PART 1
Qx
V
DD
2
nCLK
V
CLK
PP
Cross Points
V
PART 2
CMR
V
DD
Qy
2
t
sk(pp)
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
nCLK
CLK
P
ART
-
TO
-P
ART
S
KEW
V
Q0
Pulse Width
t
DD
2
Q0
V
DD
2
t
PERIOD
PD
odc =
t
PW
t
PERIOD
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
2V
0.8V
t
R
2V
0.8V
t
F
20%
80%
80%
20%
Clock
Outputs
Clock
Outputs
t
R
t
F
3.3V O
UTPUT
R
ISE
/F
ALL
T
IME
83021AMI
2.5V O
UTPUT
R
ISE
/F
ALL
T
IME
www.icst.com/products/hiperclocks.html
5
REV. B JUNE 30, 2004
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