Data Sheet
April 2012
DS3106
Line Card Timing IC
General Description
The DS3106 is a low-cost timing IC for telecom line
cards. The device accepts two reference clocks from
dual redundant system timing cards, continually
monitors both inputs, and performs manual reference
switching if the primary reference fails. The highly
programmable DS3106 supports numerous input and
output frequencies including frequencies required for
SONET/SDH, Synchronous Ethernet (1G, 10G, and
100Mbps), wireless base stations, and CMTS
systems. PLL bandwidths from 18Hz to 400Hz are
supported, and a wide variety of PLL characteristics
and device features can be configured to meet the
needs of many different applications.
The DS3106 register set is backward compatible with
Semtech’s ACS8526 line card timing IC. The DS3106
pinout is similar but not identical to the ACS8526.
♦
Advanced DPLL Technology
Features
♦
♦
♦
♦
♦
Programmable PLL Bandwidth: 18Hz to 400Hz
Manual Reference Switching
Holdover on Loss of All Input References
Frequency Conversion Among SONET/SDH,
PDH, Ethernet, Wireless, and CMTS Rates
CMOS/TTL Signal Format (≤ 125MHz)
Numerous Input Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Frame Sync: 2kHz, 4kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up
to 125MHz
One CMOS/TTL Output (≤ 125MHz)
One LVDS/LVPECL Output (≤ 312.50MHz)
Two Optional Frame-Sync Outputs: 2kHz, 8kHz
Numerous Output Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Other: 10, 10.24, 13, 30.72MHz
Frame Sync: 2kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
77.76MHz, Any Multiple of 8kHz Up to
311.04MHz, Any Multiple of 10kHz Up to
388.79MHz
Suitable Line Card IC for Stratum 3/3E/4, SMC,
SEC
Internal Compensation for Master Clock Oscillator
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Industrial Operating Temperature Range
Two Input Clocks
♦
♦
♦
Two Output Clocks
Applications
SONET/SDH, Synchronous Ethernet, PDH, and
Other Line Cards in WAN Equipment Including
MSPPs, Ethernet Switches, Routers, DSLAMs,
and Wireless Base Stations
♦
♦
♦
♦
Simplified Functional Diagram
♦
IC3
IC4
OC6 LVDS/LVPECL
DS3106
OC3
General
♦
♦
♦
♦
♦
FSYNC
MFSYNC
LOCAL
OSCILLATOR
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
64 LQFP
64 LQFP
DS3106LN
DS3106LN+
CONTROL STATUS
+Denotes
a lead(Pb)-free/RoHS-compliant package.
1
DS3106
Table of Contents
1.
2.
3.
4.
5.
5.1
5.2
5.3
5.4
5.5
6.
7.
7.1
7.2
7.3
7.4
7.5
STANDARDS COMPLIANCE ....................................................................................................... 6
APPLICATION EXAMPLE ............................................................................................................ 7
BLOCK DIAGRAM ........................................................................................................................ 7
DETAILED DESCRIPTION............................................................................................................ 8
DETAILED FEATURES ................................................................................................................. 9
I
NPUT
C
LOCK
F
EATURES
.............................................................................................................. 9
DPLL F
EATURES
.......................................................................................................................... 9
O
UTPUT
APLL F
EATURES
............................................................................................................. 9
O
UTPUT
C
LOCK
F
EATURES
........................................................................................................... 9
G
ENERAL
F
EATURES
.................................................................................................................... 9
PIN DESCRIPTIONS ................................................................................................................... 10
FUNCTIONAL DESCRIPTION .................................................................................................... 14
O
VERVIEW
................................................................................................................................. 14
D
EVICE
I
DENTIFICATION AND
P
ROTECTION
................................................................................... 14
L
OCAL
O
SCILLATOR AND
M
ASTER
C
LOCK
C
ONFIGURATION
........................................................... 14
I
NPUT
C
LOCK
C
ONFIGURATION
.................................................................................................... 15
Signal Format Configuration ................................................................................................................ 15
Frequency Configuration ...................................................................................................................... 15
Frequency Monitoring .......................................................................................................................... 16
Activity Monitoring ................................................................................................................................ 16
Selected Reference Activity Monitoring ............................................................................................... 17
7.4.1
7.4.2
7.5.1
7.5.2
7.5.3
I
NPUT
C
LOCK
M
ONITORING
......................................................................................................... 16
7.6
7.7
I
NPUT
C
LOCK
P
RIORITY AND
S
WITCHING
...................................................................................... 18
DPLL A
RCHITECTURE AND
C
ONFIGURATION
................................................................................ 19
T0 DPLL State Machine ....................................................................................................................... 20
Bandwidth ............................................................................................................................................ 23
Damping Factor .................................................................................................................................... 23
Phase Detectors ................................................................................................................................... 23
Loss-of-Lock Detection ........................................................................................................................ 24
Frequency and Phase Measurement ................................................................................................... 25
Input Jitter Tolerance ........................................................................................................................... 25
Jitter Transfer ....................................................................................................................................... 25
Output Jitter and Wander ..................................................................................................................... 25
Signal Format Configuration ................................................................................................................ 26
Frequency Configuration ...................................................................................................................... 26
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.8
O
UTPUT
C
LOCK
C
ONFIGURATION
................................................................................................ 25
7.8.1
7.8.2
7.9 M
ICROPROCESSOR
I
NTERFACE
................................................................................................... 34
7.10
R
ESET
L
OGIC
.......................................................................................................................... 37
7.11
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.......................................................................................... 37
7.12
I
NITIALIZATION
......................................................................................................................... 37
8.
8.1
8.2
8.3
8.4
REGISTER DESCRIPTIONS ....................................................................................................... 38
S
TATUS
B
ITS
.............................................................................................................................. 38
C
ONFIGURATION
F
IELDS
............................................................................................................. 38
M
ULTIREGISTER
F
IELDS
.............................................................................................................. 38
R
EGISTER
D
EFINITIONS
.............................................................................................................. 39
2
DS3106
9.
JTAG TEST ACCESS PORT AND BOUNDARY SCAN.............................................................. 74
9.1 JTAG D
ESCRIPTION
................................................................................................................... 74
9.2 JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
............................................................. 75
9.3 JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
...................................................................... 77
9.4 JTAG T
EST
R
EGISTERS
.............................................................................................................. 78
10. ELECTRICAL CHARACTERISTICS ........................................................................................... 79
10.1
10.2
10.3
10.4
10.5
10.6
11.
12.
13.
14.
15.
DC C
HARACTERISTICS
............................................................................................................ 79
I
NPUT
C
LOCK
T
IMING
............................................................................................................... 82
O
UTPUT
C
LOCK
T
IMING
........................................................................................................... 82
SPI I
NTERFACE
T
IMING
............................................................................................................ 83
JTAG I
NTERFACE
T
IMING
........................................................................................................ 85
R
ESET
P
IN
T
IMING
.................................................................................................................. 86
PIN ASSIGNMENTS.................................................................................................................... 87
PACKAGE INFORMATION ......................................................................................................... 89
THERMAL INFORMATION ......................................................................................................... 89
ACRONYMS AND ABBREVIATIONS ......................................................................................... 90
DATA SHEET REVISION HISTORY ........................................................................................... 91
3
DS3106
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 7
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 19
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 21
Figure 7-3. FSYNC 8kHz Options.............................................................................................................................. 33
Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 36
Figure 7-5. SPI Bus Transactions .............................................................................................................................. 36
Figure 9-1. JTAG Block Diagram ............................................................................................................................... 74
Figure 9-2. JTAG TAP Controller State Machine ...................................................................................................... 76
Figure 10-1. Recommended Termination for LVDS Output Pins .............................................................................. 81
Figure 10-2. Recommended Termination for LVPECL-Compatible Output Pins ...................................................... 81
Figure 10-3. SPI Interface Timing Diagram ............................................................................................................... 84
Figure 10-4. JTAG Timing Diagram ........................................................................................................................... 85
Figure 10-5. Reset Pin Timing Diagram .................................................................................................................... 86
Figure 11-1. Pin Assignment Diagram ....................................................................................................................... 88
4
DS3106
List of Tables
Table 1-1. Applicable Telecom Standards ................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 10
Table 6-2. Output Clock Pin Descriptions .................................................................................................................. 10
Table 6-3. Global Pin Descriptions ............................................................................................................................ 11
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 12
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 12
Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 13
Table 7-1. Input Clock Capabilities ............................................................................................................................ 15
Table 7-2. Input Clock Default Frequency Configuration........................................................................................... 15
Table 7-3. Locking Frequency Modes ....................................................................................................................... 15
Table 7-4. Damping Factors and Peak Jitter/Wander Gain ....................................................................................... 23
Table 7-5. Output Clock Capabilities ......................................................................................................................... 25
Table 7-6. Digital1 Frequencies ................................................................................................................................. 27
Table 7-7. Digital2 Frequencies ................................................................................................................................. 27
Table 7-8. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 28
Table 7-9. T0 APLL Frequency Configuration ........................................................................................................... 28
Table 7-10. T0 APLL2 Frequency Configuration ....................................................................................................... 28
Table 7-11. T4 APLL Frequency Configuration ......................................................................................................... 29
Table 7-12. OC3 and OC6 Output Frequency Selection ........................................................................................... 29
Table 7-13. Standard Frequencies for Programmable Outputs ................................................................................ 30
Table 7-14. T0FREQ Default Settings ....................................................................................................................... 32
Table 7-15. T4FREQ Default Settings ....................................................................................................................... 32
Table 7-16. OC6 Default Frequency Configuration ................................................................................................... 32
Table 7-17. OC3 Default Frequency Configuration ................................................................................................... 33
Table 8-1. Register Map ............................................................................................................................................ 39
Table 9-1. JTAG Instruction Codes ........................................................................................................................... 77
Table 9-2. JTAG ID Code .......................................................................................................................................... 78
Table 10-1. Recommended DC Operating Conditions .............................................................................................. 79
Table 10-2. DC Characteristics .................................................................................................................................. 79
Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 80
Table 10-4. LVDS Output Pins .................................................................................................................................. 80
Table 10-5. LVPECL Level-Compatible Output Pins ................................................................................................. 81
Table 10-6. Input Clock Timing .................................................................................................................................. 82
Table 10-7. Input Clock to Output Clock Delay ......................................................................................................... 82
Table 10-8. Output Clock Phase Alignment, Frame-Sync Alignment Mode.............................................................. 82
Table 10-9. SPI Interface Timing ............................................................................................................................... 83
Table 10-10. JTAG Interface Timing.......................................................................................................................... 85
Table 10-11. Reset Pin Timing .................................................................................................................................. 86
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................... 87
Table 13-1. LQFP Package Thermal Properties, Natural Convection....................................................................... 89
Table 13-2. LQFP Theta-JA (θ
JA
) vs. Airflow ............................................................................................................. 89
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