MC74ACT564
Octal D−Type Flip−Flop
with 3−State Outputs
The MC74ACT564 is a high−speed, low power octal flip−flop with
a buffered common Clock (CP) and a buffered common Output
Enable (OE).
The information presented to the D inputs is stored in the flip−flops
on the LOW−to−HIGH Clock (CP) transition.
The MC74ACT564 device is functionally indentical to the
MC74ACT574, but with inverted outputs.
Features
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•
Inputs and Outputs on the Opposite Sides of the Package Allowing
•
•
•
•
•
•
Easy Interface with Microprocessors
Useful as Input or Output Port for Microprocessor
Functionally Indentical to the MC74ACT574 but with Inverted
Outputs
3−State Outputs for Bus−Oriented Applications
Outputs Source/Sink 24 mA
TTL Compatible Inputs
Pb−Free Packages are Available*
1
PDIP−20
N SUFFIX
CASE 738
SOIC−20W
DW SUFFIX
CASE 751D
1
V
CC
20
O
0
19
O
1
18
O
2
17
O
3
16
O
4
15
O
5
14
O
6
13
O
7
12
CP
11
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
DEVICE MARKING INFORMATION
1
OE
2
D
0
3
D
1
4
D
2
5
D
3
6
D
4
7
D
5
8
D
6
9
D
7
10
GND
See general marking information in the device marking
section on page 5 of this data sheet.
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
PIN ASSIGNMENT
PIN
D
0
−D
7
CP
OE
O
0
−O
7
FUNCTION
Data Inputs
Clock Pulse Input
3−State Output Enable Input
3−State Outputs
CP
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Figure 2. Logic Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 3
Publication Order Number:
MC74ACT564/D
MC74ACT564
D
0
CP
C
Q
D
C
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
FUNCTION TABLE
Inputs
OE
H
H
H
H
L
L
L
L
=
=
=
=
=
NC =
H
L
X
Z
H
H
CP
H
H
D
L
H
L
H
L
H
L
H
Internal
Q
NC
NC
H
L
H
L
NC
NC
Outputs
Function
O
Z
Z
Z
Z
H
L
NC
NC
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW−to−HIGH Transition
No Change
FUNCTIONAL DESCRIPTION
The MC74ACT564 consists of eight edge−triggered
flip−flops with individual D−type inputs and 3−state
complementary outputs. The buffered clock and buffered
Output Enable are common to all flip−flops. The eight
flip−flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the
LOW−to−HIGH Clock (CP) transition. With the Output
Enable (OE) LOW, the contents of the eight flip−flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance state. Operation of the OE input does
not affect the state of the flip−flops.
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MC74ACT564
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink/Source Current
DC Supply Current per Output Pin
DC Ground Current per Output Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
Oxygen Index: 30% − 35%
PDIP
SOIC
PDIP
SOIC
(Note 1)
Parameter
Value
*0.5
to
)7.0
*0.5 v
V
I
v
V
CC
)0.5
*0.5 v
V
O
v
V
CC
)0.5
$20
$50
$50
$50
$50
*65
to
)150
260
)150
67
96
750
500
Level 1
UL 94−V0 @ 0.125 in
> 2000
> 200
> 1000
$100
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance
Above V
CC
and Below GND at 85_C (Note 5)
I
Latchup
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
T
J
I
OH
I
OL
Parameter
DC Input Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Note 7)
Junction Temperature (PDIP)
Output Current − High
Output Current − Low
V
CC
= 4.5 V
V
CC
= 5.5 V
Min
4.5
0
−40
0
0
25
10
8.0
Typ
Max
5.5
V
CC
+85
10
8.0
140
−24
24
Unit
V
V
°C
ns/V
°C
mA
mA
6. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level.
7. V
in
from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74ACT564
DC CHARACTERISTICS
T
A
= +255C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
0.6
±0.5
T
A
=
−405C to +855C
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
Conditions
V
OUT
= 0.1 V
or
V
CC
− 0.1 V
V
OUT
= 0.1 V
or
V
CC
− 0.1 V
I
OUT
= −50
mA
*V
IN
= V
IL
or V
IH
I
OH
I
OUT
= 50
mA
*V
IN
= V
IL
or V
IH
I
OL
V
I
= V
CC
, GND
V
I
= V
CC
− 2.1 V
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
24 mA
24 mA
−24 mA
−24 mA
Symbol
V
IH
Parameter
Minimum High Level Input Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
±5.0
V
IL
Maximum Low Level Input Voltage
V
OH
Minimum High Level Output Voltage
V
OL
Maximum Low Level Output Voltage
4.5
5.5
4.5
5.5
I
IN
DI
CCT
I
OZ
Maximum Input Leakage Current
Additional Max. I
CC
/Input
Maximum 3−State Current
5.5
5.5
5.5
I
OLD
I
OHD
I
CC
†Minimum Dynamic Output Current
Maximum Quiescent Supply Current
5.5
5.5
5.5
8.0
75
−75
80
mA
mA
mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS
t
r
= t
f
= 3.0 ns (For Figures and Waveforms, See Figures 4, 5, and 6.)
Symbol
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Maximum Clock Frequency
Propagation Delay
Propagation Delay
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
CP to Q
n
CP to Q
n
V
CC
*
(V)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
T
A
= +25°C
C
L
= 50 pF
Min
85
2.0
1.5
1.5
1.5
1.5
1.5
Typ
−
−
−
−
−
−
−
Max
−
10.5
9.5
9.0
8.5
10.5
8.0
T
A
= −40°C to +85°C
C
L
= 50 pF
Min
75
1.5
1.5
1.5
1.0
1.5
1.0
Max
−
11.5
10.5
9.5
9.5
11.5
8.5
MHz
ns
ns
ns
ns
ns
ns
Unit
*Voltage Range 5.0 V is 5.0 V
±0.5
V
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MC74ACT564
AC OPERATING REQUIREMENTS
Symbol
t
s
t
h
t
w
Parameter
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
C
P
Pulse Width
D
n
to C
P
D
n
to C
P
HIGH or LOW
V
CC
*
(V)
Typ
5.0
5.0
5.0
−
−
−
2.5
1.0
3.0
T
A
= +25°C
C
L
= 50 pF
T
A
= −40°C to +85°C
C
L
= 50 pF
Guaranteed Minimum
3.0
1.0
3.5
ns
ns
ns
Unit
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
CAPACITANCE
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
Parameter
Value Typ
4.5
50
Unit
pF
pF
Test Conditions
V
CC
= 5.0 V
V
CC
= 5.0 V
ORDERING INFORMATION
Device
MC74ACT564N
MC74ACT564NG
MC74ACT564DWR2
MC74ACT564DWR2G
Package
PDIP−20
PDIP−20
(Pb−Free)
SOIC−20
SOIC−20
(Pb−Free)
1000 / Tape & Reel
18 Units / Rail
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP−20
SOIC−20W
20
20
MC74ACT564N
AWLYYWWG
1
1
ACT564
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
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