Operating Temperature Range ............................-40ºC to +85ºC
Junction Temperature ......................................................
+150ºC
Storage Temperature Range .............................-55ºC to +125ºC
Lead Temperature (soldering, 10s) .................................
+300ºC
Soldering Temperature (reflow) .......................................
+260ºC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TSOC
Junction-to-Ambient Thermal Resistance (θ
JA
) .....126.7°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............37°C/W
TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ..........60°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............11°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(T
A
= -40ºC to +85ºC.) (Note 2)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching Threshold
Input Low Voltage
Low-to-High Switching Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
Time Slot Duration
Reset Low Time
Reset High Time
Presence Detect Sample Time
IO PIN: 1-Wire WRITE
Write-Zero Low Time
Write-One Low Time
IO PIN: 1-Wire READ
Read Low Time
Read Sample Time
t
RL
t
MSR
(Notes 3, 18)
(Notes 3, 18)
1
t
RL
+ d
2-
d
2
µs
µs
t
W0L
t
W1L
(Notes 3, 17)
(Notes 3, 17)
8
1
16
2
µs
µs
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
t
REC
t
SLOT
t
RSTL
t
RSTH
t
MSP
(Note 3)
V
PUP
= 3.3V ±10% (Note 4)
(Notes 5, 6)
IO pin at V
PUP
(Notes 6, 7, 8)
(Notes 3, 9)
(Notes 6, 7, 10)
(Notes 6, 7, 11)
I
OL
= 4mA (Note 12)
R
PUP
= 1500Ω (Notes 3, 13)
(Notes 3, 14)
(Note 3)
(Note 15)
(Notes 3, 16)
5
13
48
48
8
10
80
0.75 x V
PUP
0.3
0.4
2.97
300
1500
5
0.65 x V
PUP
0.3
50
3.63
1500
V
Ω
pF
µA
V
V
V
V
V
µs
µs
µs
µs
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
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Maxim Integrated
│
2
ABRIDGED DATA SHEET
DS28E35
DeepCover Secure Authenticator with
1-Wire ECDSA and 1Kb User EEPROM
Electrical Characteristics (continued)
(T
A
= -40ºC to +85ºC.) (Note 2)
PARAMETER
EEPROM
Programming Current
Programming Time Unit
Write/Erase Cycling Endurance
Data Retention
ECDSA ENGINE
Computation Current
Key Pair Computation Time
Signature Computation Time
I
ECE
t
GKP
t
GPS
Refer to the full data sheet.
mA
ms
ms
I
PROG
t
PROG
N
CY
t
DR
V
PUP
= 3.63V (Notes 6, 19)
Refer to the full data sheet.
T
A
= +85ºC (Notes 21, 22)
T
A
= +85ºC (Notes 23, 24, 25)
100k
10
1
mA
ms
—
years
SYMBOL
CONDITIONS
MIN
TYP
MAX
Note 2:
Limits are 100% production tested at T
A
= +25ºC and T
A
= +85ºC. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are at T
A
= +25ºC.
Note 3:
System requirement.
Note 4:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 5:
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 6:
Guaranteed by design and/or characterization only; not production tested.
Note 7:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values
of V
TL
, V
TH
, and V
HY
.
Note 8:
Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 9:
The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic-zero level.
Note 10:
Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 11:
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic-zero.
Note 12:
The I-V characteristic is linear for voltages less than 1V.
Note 13:
Applies to a single device attached to a 1-Wire line. 100% production tested at T
A
= +85ºC, +25ºC, and -40ºC.
Note 14:
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 15:
An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 16:
Interval after t
RSTL
during which a bus master can read a logic-zero on IO if there is a
DS28E35
present. The power-up
presence detect pulse could be outside this interval, but is complete within 2ms after power-up.
Note 17:
ε in Figure
11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 18:
δ in Figure
11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 19:
Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to 2.5V.
Note 20: Refer to the full data sheet.
Note 21:
Write-cycle endurance is tested in compliance with JESD47G.
Note 22:
Not 100% production tested; guaranteed by reliability monitor sampling.
Note 23:
Data retention is tested in compliance with JESD47G.
Note 24:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 25:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated
temperatures is not recommended.
Note 26: Refer to the full data sheet.
Note 27: Refer to the full data sheet.
Note 28: Refer to the full data sheet.
www.maximintegrated.com
Maxim Integrated
│
3
ABRIDGED DATA SHEET
DS28E35
DeepCover Secure Authenticator with
1-Wire ECDSA and 1Kb User EEPROM
Pin Configuration
TOP VIEW
N.C. N.C. N.C. N.C.
+
GND
IO
N.C.
1
2
3
8
7
6
5
DS28E35
6 N.C.
5 N.C.
4 N.C.
DS28E35
28E35
ymrrF
EP
TSOC
+
1
IO
2
3
4
GND N.C. N.C.
PACKAGE SIZES NOT DRAWN TO SCALE
TDFN
(2mm x 3mm)
Pin Description
PIN
TSOC
1
2
3–6
—
TDFN-EP
2
1
3–8
EP
NAME
GND
IO
N.C.
EP
Ground Reference
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Not Connected
Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A
Brief Introduction
for additional information.
FUNCTION
www.maximintegrated.com
Maxim Integrated
│
4
ABRIDGED DATA SHEET
DS28E35
DeepCover Secure Authenticator with
1-Wire ECDSA and 1Kb User EEPROM
Package Information
PIN-PACKAGE
8 TDFN-EP* (2.5k pcs)
6 TSOC
6 TSOC (4k pcs)
Ordering Information
PART
DS28E35Q+T**
DS28E35P+
DS28E35P+T
TEMP RANGE
-40ºC to +85ºC
-40ºC to +85ºC
-40ºC to +85ºC
For the latest package outline information and land patterns
(footprints), go to
www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
6 TSOC
8 TDFN-EP
PACKAGE
CODE
D6+1
T823+1
OUTLINE
NO.
21-0382
21-0174
LAND
PATTERN NO.
90-0321
90-0091
+Denotes lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP
= Exposed pad.
**Future product—contact factory for availability.
Note to readers:
This document is an abridged version of the full data sheet. Additional device information is available
only in the full version of the data sheet. To request the full data sheet, go to
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