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DS1005S-200+T&R

Description
Delay Lines / Timing Elements
Categorylogic    logic   
File Size62KB,6 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
Environmental Compliance
Download Datasheet Parametric View All

DS1005S-200+T&R Overview

Delay Lines / Timing Elements

DS1005S-200+T&R Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMaxim
Parts packaging codeSOIC
package instructionSOP, SOP16,.4
Contacts16
Reach Compliance Codecompliant
Other featuresBOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT
seriesCMOS/TTL
Input frequency maximum value (fmax)3.125 MHz
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.9 mm
Logic integrated circuit typeSILICON DELAY LINE
Humidity sensitivity level1
Number of functions1
Number of taps/steps5
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)75 mA
programmable delay lineNO
Prop。Delay @ Nom-Sup200 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Total delay nominal (td)200 ns
width3.9 mm
Base Number Matches1
DS1005
5-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon time delay
5 taps equally spaced
Delay tolerance ±2 ns or ±3%, whichever is
greater
Stable and precise over temperature and
voltage range
Leading and trailing edge accuracy
Economical
Auto-insertable, low profile
Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
Tape and reel available for surface-mount
Low-power CMOS
TTL/CMOS compatible
Vapor phase, IR and wave solderability
Custom delays available
Quick turn prototypes
Extended temperature range available
IN
NC
NC
TAP 2
NC
TAP 4
GND
PIN ASSIGNMENT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
NC
TAP 1
NC
TAP 3
NC
TAP 5
IN
NC
NC
TAP 2
NC
TAP 4
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
NC
TAP 1
NC
TAP 3
NC
TAP 5
DS1005 14-Pin DIP (300-mil)
See Mech. Drawings Section
DS1005S 16-Pin SOIC
(300-mil)
See Mech. Drawings Section
8
7
6
5
V
CC
TAP 1
TAP 3
TAP 5
IN
TAP 2
TAP 4
GND
1
2
3
4
DS1005M 8-Pin DIP (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-TAP 5
V
CC
GND
NC
IN
- TAP Output Number
- +5 Volts
- Ground
- No Connection
- Input
DESCRIPTION
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns
to 250 ns, with an accuracy of
±2
ns or
±3%,
whichever is greater. This device is offered in a standard 14-
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call (972) 371–4348.
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