849N212CKI-005LF datasheet, PDF

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849N212CKI-005LF: DescriptionClock Synthesizer / Jitter Cleaner Frequency Translator IC; Categorysemiconductor Analog mixed-signal IC; File Size693KB，38 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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849N212CKI-005LF Overview

Clock Synthesizer / Jitter Cleaner Frequency Translator IC

849N212CKI-005LF Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	IDT (Integrated Device Technology)
Product Category	Clock Synthesizer / Jitter Cleaner
RoHS	Details
Number of Outputs	2 Output
Output Level	LVCMOS, LVDS, LVPECL
Max Output Freq	250 MHz
Input Level	HCSL, LVDS, LVHSTL, LVPECL
Maximum Input Frequency	710 MHz
Supply Voltage - Max	3.465 V
Supply Voltage - Min	3.135 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	VFQFN-40
Packaging	Tray
Operating Supply Current	280 mA
Factory Pack Quantity	490

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FemtoClock® NG Universal Frequency

Translator

General Description

The ICS849N212I is a highly flexible FemtoClock® NG general

purpose, low phase noise Frequency Translator / Synthesizer with

alarm and monitoring functions suitable for networking and

communications applications. It is able to generate any output

frequency in the 1MHz - 250MHz range (see Table 3 for details). A

wide range of input reference clocks and a range of low-cost

fundamental mode crystal frequencies may be used as the source

for the output frequency.

The ICS849N212I has three operating modes to support a very

broad spectrum of applications:

1) Frequency Synthesizer

ICS849N212I

DATA SHEET

Features

•

Fourth generation FemtoClock® NG technology

Universal Frequency Translator/Frequency Synthesizer

Two outputs

•

One programmable as LVPECL or LVDS

One LVCMOS

Both outputs may be set to use 2.5V or 3.3V output levels

Programmable output frequency: 1.0MHz to 250MHz

Two differential inputs support the following input types: LVPECL,

LVDS, LVHSTL, HCSL

Input frequency range: 8kHz - 710MHz

Crystal input frequency range: 16MHz - 40MHz

Two factory-set register configurations for power-up default state

•

Synthesizes output frequencies from a 16MHz - 40MHz

fundamental mode crystal.

Fractional feedback division is used, so there are no

requirements for any specific crystal frequency to produce the

desired output frequency with a high degree of accuracy.

Applications: PCI Express, Computing, General Purpose

Translates any input clock in the 16MHz - 710MHz frequency

range into any supported output frequency.

This mode has a high PLL loop bandwidth in order to track input

reference changes, such as Spread-Spectrum Clock

modulation, so it will not attenuate much jitter on the input

reference.

Applications: Networking & Communications.

Translates any input clock in the 8kHz - 710MHz frequency

range into any supported output frequency.

This mode supports PLL loop bandwidths in the 10Hz - 580Hz

range and makes use of an external crystal to provide

significant jitter attenuation.

2) High-Bandwidth Frequency Translator

•

Power-up default configuration pin or register selectable

Configurations customized via One-Time Programmable ROM

Settings may be overwritten after power-up via I

C Serial interface for register programming

RMS phase jitter at 125MHz, using a 40MHz crystal

(12kHz - 20MHz): 558fs (typical), Low Bandwidth Mode (FracN)

RMS phase jitter at 125MHz, using a 100MHz input clock

(12kHz - 20MHz): 388fs (typical), High Bandwidth Mode

(Integer FB)

Output supply voltage modes:

CCA

CCO

3.3V/3.3V/3.3V

3.3V/3.3V/2.5V (LVPECL only)

2.5V/2.5V/2.5V

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

3) Low-Bandwidth Frequency Translator

•

This device provides two factory-programmed default power-up

configurations burned into One-Time Programmable (OTP) memory.

The configuration to be used is selected by the CONFIG pin. The two

configurations are specified by the customer and are programmed by

IDT during the final test phase from an on-hand stock of blank

devices. The two configurations may be completely independent of

one another.

One usage example might be to install the device on a line card with

two optional daughter cards: an OC-3 option (configuration 0)

requiring a 155.52MHz LVDS clock translated from a 19.44MHz input

and a Gigabit Ethernet option (configuration 1) requiring a 125MHz

LVPECL clock translated from the same 19.44MHz input reference.

To implement other configurations, these power-up default settings

can be overwritten after power-up using the I

C interface and the

device can be completely reconfigured. However, these settings

would have to be re-written each time the device powers-up.

Pin Assignment

XTALBAD

CLK1BAD

CLK_ACTIVE

HOLDOVER

CLK0BAD

CCA

LF1

LF0

XTAL_IN

XTAL_OUT

CLK_SEL

CLK0

nCLK0

CLK1

nCLK1

40 39 38 37 36 35 34 33 32 31

LOCK_IND

OE0

nQ0

CCO

OE1

ICS849N212I

40 Lead VFQFN

6mm x 6mm x 0.925mm

K Package

Top View

11 12 13 14 15 16 17 18 19 20

CONFIG

S_A1

S_A0

PLL_BYPASS

SDATA

SCLK

ICS849N212CKI REVISION B NOVEMBER 19, 2012

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Product Attribute	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value
Manufacturer	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Product Category	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner	Clock Synthesizer / Jitter Cleaner
RoHS	Details	Details	Details	Details	Details	Details	Details	Details
Packaging	Tray	Reel	Reel	Reel	Reel	Tray	Tray	Tray
Factory Pack Quantity	490	5000	1000	5000	5000	490	490	490
Number of Outputs	2 Output	-	2 Output	2 Output	2 Output	2 Output	2 Output	2 Output
Output Level	LVCMOS, LVDS, LVPECL	-	LVCMOS, LVDS, LVPECL	LVCMOS, LVDS, LVPECL	LVCMOS, LVDS, LVPECL	LVCMOS, LVDS, LVPECL	LVCMOS, LVDS, LVPECL	LVCMOS, LVDS, LVPECL
Max Output Freq	250 MHz	-	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz
Input Level	HCSL, LVDS, LVHSTL, LVPECL	-	HCSL, LVDS, LVHSTL, LVPECL	HCSL, LVDS, LVHSTL, LVPECL	HCSL, LVDS, LVHSTL, LVPECL	HCSL, LVDS, LVHSTL, LVPECL	HCSL, LVDS, LVHSTL, LVPECL	HCSL, LVDS, LVHSTL, LVPECL
Maximum Input Frequency	710 MHz	-	710 MHz	710 MHz	710 MHz	710 MHz	710 MHz	710 MHz
Supply Voltage - Max	3.465 V	-	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Supply Voltage - Min	3.135 V	-	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Minimum Operating Temperature	- 40 C	-	- 40 C	- 40 C	- 40 C	- 40 C	- 40 C	- 40 C
Maximum Operating Temperature	+ 85 C	-	+ 85 C	+ 85 C	+ 85 C	+ 85 C	+ 85 C	+ 85 C
Mounting Style	SMD/SMT	-	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Package / Case	VFQFN-40	-	VFQFN-40	VFQFN-40	VFQFN-40	VFQFN-40	VFQFN-40	VFQFN-40
Operating Supply Current	280 mA	-	280 mA	280 mA	280 mA	280 mA	280 mA	280 mA

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