a
FEATURES
Low Cost
Replaces 8 Potentiometers
50 kHz 4-Quadrant Multiplying Bandwidth
Low Zero Output Error
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
±3
V Output Swing
Midscale Preset, Zero Volts Out
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Vertical Deflection Amplitude Adjustment
Waveform Generation and Modulation
V
DD
8-Bit Octal, 4-Quadrant
Multiplying, CMOS TrimDAC
AD8842
FUNCTIONAL BLOCK DIAGRAM
DECODED
ADDRESS
8
LOGIC
DATA
4
SDI
8
SERIAL
REGISTER
8X 8
DAC
R
E
G
I
S
T
E
R
S
8
DAC A
V
OUT
A
V
IN
A
G
LD
AD8842
V
IN
H
8
G
DAC H
V
OUT
H
CLK
GND
V
SS
SDO
PR
GENERAL DESCRIPTION
The AD8842 provides eight general purpose digitally controlled
voltage adjustment devices. The TrimDAC® capability allows
replacement of the mechanical trimmer function in new designs.
The AD8842 is ideal for ac or dc gain control of up to 50 kHz
bandwidth signals. The four-quadrant multiplying capability is
useful for signal inversion and modulation often found in video
vertical deflection circuitry.
Internally the AD8842 contains eight voltage output digital-to-
analog converters, each with separate voltage inputs. A new
current conveyor amplifier design performs the four-quadrant
multiplying function with a single amplifier at the output of the
current steering digital-to-analog converter. This approach of-
fers an improved constant input resistance performance versus
previous voltage switched DACs used in TrimDAC circuits,
eliminating the need for additional input buffer amplifiers.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire serial
input digital interface. Twelve data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 4 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. A serial data output pin
at the opposite end of the serial register allows simple daisy
chaining in multiple DAC applications without additional exter-
nal decoding logic.
TrimDAC is a registered trademark of Analog Devices, Inc.
The current conveyor amplifier is a patented circuit belonging to Analog
Devices, Inc.
The AD8842 consumes only 95 mW from
±
5 V power supplies.
For single 5 V supply applications consult the DAC-8841. The
AD8842 is pin compatible with the 1 MHz multiplying band-
width DAC8840. The AD8842 is available in 24-pin plastic
DIP and surface mount SOL-24 packages.
R
V
IN
R
V
OUT
V
OUT
= V
IN
• (D/128 – 1)
Figure 1. Functional Circuit of One 4-Quadrant
Multiplying Channel
CURRENT CONVEYOR
AMPLIFIER
REF
D
256
R
V
IN
R
V
IN
R
I1
I2
= V
IN
V
OUT
(D/128–1)
V
IN
(1- D)
256
R
Figure 2. Actual Current Conveyor Implementation of
Multiplying DAC Channel
REV.
A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel:
781/329-4700
Fax:
781/461-3113
AD8842–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(V
Parameter
Symbol
DD
= +5 V, V
SS
= –5 V, All V
IN
x = +3 V, T
A
= –40°C to +85°C, unless otherwise noted.)
Min
8
Typ
Max
Units
Bits
LSB
LSB
LSB
mV
µV/°C
V
kΩ
pF
V
mA
pF
kHz
V/µs
V/µs
%
nV/√Hz
µs
µs
dB
nV-s
14
13
135
0.01
5.25
mA
mA
mW
%/%
V
V
V
µA
pF
Conditions
STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H
Resolution
N
Integral Nonlinearity Error
INL
Differential Nonlinearity
DNL
All Devices Monotonic
Full-Scale Gain Error
G
FSE
PR
= 0, Sets D = 80
H
Output Offset
V
BZE
Output Offset Drift
TCV
BZ
PR
= 0, Sets D = 80
H
VOLTAGE INPUTS—Applies to All Inputs V
IN
x
IVR
Input Voltage Range
1
Input Resistance
R
IN
Input Capacitance
C
IN
DAC OUTPUTS—Applies to All Outputs V
OUT
x
OVR
Voltage Range
1
Output Current
I
OUT
Capacitive Load
C
L
R
L
= 10 kΩ
∆V
OUT
< 1.5 LSB
No Oscillation
±
0.2
±
0.4
2
5
5
±
4
19
9
±
4
500
±
1
±
1
25
±
3
12
±
3
±
3
DYNAMIC PERFORMANCE—Applies to All DACs
GBW
V
IN
x =
±
3 V
P
, R
L
= 2 kΩ, C
L
= 10 pF
Full Power Gain Bandwidth
1
Slew Rate
Measured 10% to 90%
Positive
SR+
∆V
OUT
x = +5.5 V
Negative
SR–
∆V
OUT
x = –5.5 V
Total Harmonic Distortion
THD
V
IN
x = 4 V p-p, D = FF
H
, f = 1 kHz,
f
LPF
= 80 kHz, R
L
= 1 kΩ
f = 1kHz, V
IN
= 0 V
Spot Noise Voltage
e
N
±
1 LSB Error Band, D = 00
H
to FF
H
Output Settling Time
t
S
D = FF
H
to 00
H
Measured Between Adjacent
Channel-to-Channel Crosstalk
C
T
Channels, f = 100 kHz
Digital Feedthrough
Q
V
IN
x = 0 V, D = 0 to 255
10
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Power Dissipation
2
Power Supply Rejection
Power Supply Range
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
DIGITAL OUTPUT
Logic High
Logic Low
TIMING SPECIFICATIONS
1
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
Load Edge to Next Clock Edge
I
DD
I
SS
P
DISS
PSRR
PSR
V
IH
V
IL
I
L
C
IL
PR
= 0 V
PR
= 0 V
PR
= 0 V,
∆V
DD
=
±
5%
V
DD
, |V
SS
|
10
0.5
1.0
50
1.0
1.8
0.01
78
2.9
5.4
72
5
10
9
95
0.0001
5.00
4.75
2.4
0.8
±
10
7
Offset Binary
I
OH
= –0.4 mA
I
OL
= 1.6 mA
3.5
0.4
60
40
20
80
70
50
30
60
V
OH
V
OL
t
CH
, t
CL
t
DS
t
DH
t
PD
t
LD
t
PR
t
CKLD
t
LDCK
V
V
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Guaranteed by design, not subject to production test.
2
Calculated limit = 5 V
×
(I
DD
+ I
SS
).
Specifications subject to change without notice.
–2–
REV.
A
AD8842
1
SDI
CLK
LD
V
OUT
0
1
0
1
0
+3V
0V
DAC REGISTER LOAD
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DETAIL SERIAL DATA INPUT TIMING (PR = “1”)
1
SDI
(DATA IN) 0
1
SDO
(DATA OUT) 0
CLK
1
0
Ax or Dx
t
DS
t
DH
t
PD
t
CH
t
CL
1
LD
0
V
OUT
+3V
0V
t
CKLD
t
LD
t
S
±1
LSB ERROR BAND
t
LDCK
±1
LSB
PRESET TIMING
1
0
t
PR
t
S
±1
LSB ERROR BAND
PR
V
OUT
+3V
0V
±1
LSB
Figure 3. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
V
IN
x to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
, V
SS
V
OUT
x to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
, V
SS
Short Circuit I
OUT
x to GND . . . . . . . . . . . . . . . . . Continuous
Digital Input & Output Voltage to GND . . . . . . . . . . V
DD
, 0 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
Max) . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . . (T
J
Max–T
A
)/θ
JA
Thermal Resistance
θ
JA,
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8842 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV.
A
–3–
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