MC74LVX4052
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVX4052 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from V
CC
to V
EE
).
The LVX4052 is similar in pinout to the high−speed HC4052A and
the metal−gate MC14052B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pull−up resistors, they are compatible with
LSTTL outputs.
This device has been designed so the ON resistance (R
ON
) is more
linear over input voltage than the R
ON
of metal−gate CMOS analog
switches and High−Speed CMOS analog switches.
Features
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SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
V
CC
16
X2
15
X1
14
X
13
X0
12
X3
11
A
10
B
9
•
•
•
•
•
1
Y0
2
Y2
3
Y
4
Y3
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Analog Power Supply Range (V
CC
− V
EE
) =
*3.0
V to
)3.0
V
Digital (Control) Power Supply Range (V
CC
− GND) = 2.5 to 6.0 V
5
6
7
8
Y1 Enable V
EE
GND
MARKING DIAGRAMS
16
LVX4052G
AWLYWW
1
SOIC−16
Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
•
Low Noise
Split Supplies up to
±3.0
V
•
Break−Before−Make Circuitry
•
These Devices are Pb−Free and are RoHS Compliant
FUNCTION TABLE
Control Inputs
Select
Enable
L
L
L
L
H
X = Don’t Care
B
L
L
H
H
X
A
L
H
L
H
X
ON Channels
Y0
Y1
Y2
Y3
NONE
X0
X1
X2
X3
•
Designed to Operate on a Single Supply with V
EE
= GND, or Using
16
LVX
4052
ALYWG
G
1
TSSOP−16
LVX4052
A
WL, L
Y
WW, W
G or
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 7
Publication Order Number:
MC74LVX4052/D
MC74LVX4052
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
1
5
2
4
10
9
6
12
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y SWITCH
3
Y
CHANNEL‐SELECT
INPUTS
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
ENABLE
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch.
Figure 1. Logic Diagram
Double−Pole, 4−Position Plus Common Off
MAXIMUM RATINGS
Symbol
V
EE
V
CC
V
IS
V
IN
I
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
Negative DC Supply Voltage
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage
DC Current, Into or Out of Any Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air,
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 125°C (Note 4)
SOIC
TSSOP
SOIC
TSSOP
(Referenced to GND)
Parameter
(Referenced to GND)
(Referenced to GND)
(Referenced to V
EE
)
Value
Unit
V
V
V
V
mA
_C
_C
_C
°C/W
mW
*
7.0 to
)0.5
*
0.5 to
)7.0
*
0.5 to
)7.0
V
EE
*
0.5 to V
CC
)0.5
*
0.5 to 7.0
±20
*
65 to
)150
260
)150
143
164
500
450
Level 1
UL 94−V0 @ 0.125 in
u2000
u200
u1000
±300
V
I
LATCHUP
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
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MC74LVX4052
RECOMMENDED OPERATING CONDITIONS
Symbol
V
EE
V
CC
V
IS
V
IN
T
A
t
r
, t
f
Negative DC Supply Voltage
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
= 3.0 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
(Note 5) (Referenced to GND)
Parameter
(Referenced to GND)
(Referenced to GND)
(Referenced to V
EE
)
Min
Max
GND
6.0
6.0
V
CC
6.0
125
100
20
Unit
V
V
V
V
_C
ns/V
*
6.0
2.5
2.5
V
EE
0
*
55
0
0
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
T
J
= 130_C
T
J
= 120_C
T
J
= 100_C
T
J
= 110_C
T
J
= 90_C
T
J
= 80_C
100
TIME, YEARS
1
1
10
1000
Figure 2. Failure Rate vs. Time Junction Temperature
DC CHARACTERISTICS − Digital Section
(Voltages Referenced to GND)
V
CC
V
2.5
3.0
4.5
6.0
2.5
3.0
4.5
6.0
V
IN
= 6.0 or GND
Channel Select, Enable
and V
IS
= V
CC
or GND
0 V to 6.0 V
6.0
Guaranteed Limit
*55
to 25°C
1.90
2.10
3.15
4.2
0.6
0.9
1.35
1.8
$0.1
4.0
v85°C
1.90
2.10
3.15
4.2
0.6
0.9
1.35
1.8
$1.0
40
v125°C
1.90
2.10
3.15
4.2
0.6
0.9
1.35
1.8
$1.0
80
Unit
V
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Condition
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
V
I
IN
I
CC
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
mA
mA
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3
MC74LVX4052
DC ELECTRICAL CHARACTERISTICS − Analog Section
V
CC
V
3.0
4.5
3.0
3.0
4.5
3.0
5.5
+3.0
5.5
+3.0
5.5
+3.0
V
EE
V
0
0
*
3.0
0
0
*
3.0
0
−3.0
0
−3.0
0
−3.0
Guaranteed Limit
*55
to 25°C
86
37
26
15
13
10
0.1
0.1
0.2
0.2
0.2
0.2
v85_C
108
46
33
20
18
15
0.5
0.5
2.0
2.0
2.0
2.0
v125_C
120
55
37
20
18
15
1.0
1.0
4.0
4.0
4.0
4.0
mA
Unit
W
Symbol
R
ON
Parameter
Maximum “ON” Resistance
Test Conditions
V
IN
= V
IL
or V
IH
V
IS
=
½
(V
CC
− V
EE
)
|I
S
| = 2.0 mA
(Figure 3)
V
IN
= V
IL
or V
IH
V
IS
=
½
(V
CC
− V
EE
)
|I
S
| = 2.0 mA
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 3)
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 4)
V
in
= V
IL
or V
IH
;
Switch−to−Switch =
V
CC
or GND; (Figure 5)
ΔR
ON
Maximum Difference in “ON” Resist-
ance Between Any Two Channels in
the Same Package
Maximum Off−Channel Leakage
Current, Any One Channel
Maximum Off−Channel
Leakage Current,
Common Channel
W
I
off
mA
I
on
Maximum On−Channel
Leakage Current,
Channel−to−Channel
AC CHARACTERISTICS
(Input t
r
= t
f
= 3 ns)
Guaranteed Limit
V
CC
V
3.0
4.5
3.0
V
EE
V
0.0
0.0
*
3.0
*55
to 25_C
Min
1.0
1.0
1.0
Typ*
6.5
5.0
3.5
v85_C
−
−
−
v125_C
−
−
−
Unit
ns
Symbol
t
BBM
Parameter
Minimum Break−Before−Make Time
Test Conditions
V
IN
= V
IL
or V
IH
V
IS
= V
CC
R
L
= 300
W,
C
L
= 35 pF
(Figures 11 and 12)
*Typical Characteristics are at 25_C.
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 3 ns)
Guaranteed Limit
V
CC
V
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
V
EE
V
0
0
0
*
3.0
0
0
0
*
3.0
0
0
0
*
3.0
*
55 to 25°C
Min
Typ
Max
40
28
23
23
40
28
23
23
40
28
23
23
v85°C
Min
Max
45
30
25
25
45
30
25
25
45
30
25
25
v125°C
Min
Max
50
35
30
28
50
35
30
28
50
35
30
28
Unit
ns
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay,
Channel−Select to Analog Output
(Figures 15 and 16)
Maximum Propagation Delay, Enable to
Analog Output (Figures 13 and 14)
t
PLZ
,
t
PHZ
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable to
Analog Output (Figures 13 and 14)
ns
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
C
IN
C
I/O
Power Dissipation Capacitance (Figure 17) (Note 6)
Maximum Input Capacitance, Channel−Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
45
10
10
10
1.0
pF
pF
pF
6. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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MC74LVX4052
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0 V)
V
CC
V
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
5.0
3.0
V
EE
V
0.0
0.0
0.0
*
3.0
0.0
0.0
0.0
*
3.0
0.0
0.0
0.0
*
3.0
Typ
25°C
80
80
80
80
Unit
MHz
Symbol
BW
Parameter
Maximum On−Channel Bandwidth or
Minimum Frequency Response
Condition
V
IS
=
½
(V
CC
− V
EE
)
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 6)
f = 1 MHz; V
IS
=
½
(V
CC
− V
EE
)
Adjust Network Analyzer output to 10 dBm on
each output from the power splitter
(Figures 7 and 8)
V
IS
=
½
(V
CC
− V
EE
)
Adjust Network Analyzer output to 10 dBm on
each output from the power splitter
(Figure 10)
V
IN
= V
CC
to V
EE,
f
IS
= 1 kHz, t
r
= t
f
= 3 ns
R
IS
= 0
W,
C
L
= 1000 pF, Q = C
L
*
ΔV
OUT
(Figure 9)
f
IS
= 1 MHz, R
L
= 10 KW, C
L
= 50 pF,
V
IS
= 5.0 V
PP
sine wave
V
IS
= 6.0 V
PP
sine wave
(Figure 18)
V
ISO
Off−Channel Feedthrough Isolation
*
70
*
70
*
70
*
70
*
2
*
2
*
2
*
2
9.0
12
dB
V
ONL
Maximum Feedthrough On Loss
dB
Q
Charge Injection
*
3.0
0.0
pC
THD
Total Harmonic Distortion THD + Noise
%
6.0
3.0
*
3.0
0.0
0.10
0.05
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
*
)
MINI
COMPUTER
DC ANALYZER
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 3. On Resistance, Test Set−Up
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