CS1610/11
CS1612/13
Resonant Mode AC/DC Dimmable LED Driver IC
Features
& Description
• Best-in-Class Dimmer Compatibility
-
Leading-edge (TRIAC) Dimmers
-
Trailing-edge Dimmers
-
Digital Dimmers (with Integrated Power Supply)
Overview
The CS1610/11/12/13 is a digital control IC engineered to deliver
a high-efficiency, cost-effective, flicker-free, phase-dimmable,
solid-state lighting (SSL) solution for the incandescent lamp
replacement market. The CS1610/11 is designed to control a
quasi-resonant flyback topology. The CS1612/13 is designed to
control a buck topology. The CS1610/12 and CS1611/13 are
designed for 120VAC and 230VAC line voltage applications,
respectively.
The CS1610/11/12/13 integrates a critical conduction mode
(CRM) boost converter that provides power factor correction and
dimmer compatibility with a constant output current, quasi-
resonant second stage. An adaptive dimmer compatibility
algorithm controls the boost stage and dimmer compatibility
operation mode to enable flicker-free operation to <2% output
current with leading-edge, trailing-edge, and digital dimmers
(dimmers with an integrated power supply).
•
•
•
•
•
•
•
•
•
•
•
•
Up to 85% Efficiency
Flicker-free Dimming
<2% Minimum Dimming Level
Temperature Compensated LED Current
Quasi-resonant Second Stage with Constant-current
Output
-
Flyback and Buck
Fast Startup
Tight LED Current Regulation: Better than ±5%
Primary-side Regulation (PSR)
>0.9 Power Factor
IEC-61000-3-2 Compliant
Soft Start
Protections:
-
Output Open/Short
-
Current-sense Resistor Open/Short
-
External Overtemperature Using NTC
Applications
& Description
•
•
•
•
Dimmable Retrofit LED Lamps
Dimmable LED Luminaries
Offline LED Drivers
Commercial Lighting
Ordering Information
See
page 14
.
L1
V
rect
L2
D6
R8
R10
V
B S T
C8
Z2
T1
D8
LED+
C9
LED-
C3
R2
R3
R4
R5
D3
C5
C6
R6
R7
1
BSTAUX
16
R9
D7
BSTOUT
3
Q3
BR1
BR1
D4
CLAMP
R1
2
C2
D2
Q2
5
IAC
AC
Mains
C1
CS1610 /11
SOURCE
GD
FBAUX
13
15
11
10
R
S
Q4
R12
Q1
D5
14
FBSENSE
VDD
eOTP
8
C7
IPK
SGND
R
IP K
4
GND
12
FBGAIN
9
R
FB GA IN
NTC
R13
BR1
BR1
D1
Z1
C4
C
NTC
R11
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright
Cirrus Logic, Inc. 2011
(All Rights Reserved)
DEC’11
DS929F1
CS1610/11/12/13
1. INTRODUCTION
15k
BSTOUT
IAC
16
I
ref
MUX
Voltage
Regulator
POR
+
14
VDD
ADC
2
15k
-
V
S T(th )
V
S TP(th )
V
Z
13
GD
GND
BSTAUX
1
V
FB ZCD(th)
+
-
Boost ZCD
t
B S TZCD
t
LE B
OLP
OCP
-
+
12
V
OLP (th)
V
OCP (th )
11
SOURCE
5
V
S OURCE(th )
+
+
-
-
Peak
Control
+
I
S OURCE
-
DAC
FBSENSE
V
P k_Max (th)
SGND
IPK
eOTP
FBGAIN
4
Output Open
VDD
8
I
CONNE CT
10
MUX
+
t
FB ZCD
Second Stage ZCD
-
+
V
OV P (th )
15
-
V
FB ZCD(th)
FBAUX
VDD
9
V
CONNE CT(th )
-
I
CLA MP
3
+
CLAMP
Figure 1. CS1610/11/12/13 Block Diagram
A typical schematic using the CS1610/11 for flyback
applications is shown on the previous page.
Startup current is provided from a patent-pending, external
high-voltage source-follower network. In addition to providing
startup current, this unique topology is integral in providing
compatibility with digital dimmers by ensuring VDD power is
always available to the IC. During steady-state operation, an
auxiliary winding on the boost inductor back-biases the
source-follower circuit and provides steady-state operating
current to the IC to improve system efficiency.
The rectified input voltage is sensed as a current into pin IAC
and is used to control the adaptive dimmer compatibility
algorithm and extract the phase of the input voltage for output
dimming control. During steady-state operation, the external
high-voltage, source-follower circuit is source-switched in
critical conduction mode (CRM) to boost the input voltage.
This allows the boost stage to maintain good power factor,
provides dimmer compatibility, reduces bulk capacitor ripple
current, and provides a regulated input voltage to the second
stage.
The output voltage of the CRM boost is sensed by the current
into the boost output voltage sense pin (BSTOUT). The quasi-
resonant second stage is implemented with peak-current
mode primary-side control, which eliminates the need for
additional components to provide feedback from the
secondary and reduces system cost and complexity.
Voltage across an external user-selected resistor is sensed
through pin FBSENSE to control the peak current through the
second stage inductor. Leading-edge and trailing-edge
blanking on pin FBSENSE prevents false triggering.
Pin FBAUX is used to sense the second stage inductor
demagnetization to ensure quasi-resonant switching of the
output stage.
When an external negative temperature coefficient (NTC)
thermistor is connected to the eOTP pin, the
CS1610/11/12/13 monitors the system temperature, allowing
the controller to reduce the output current of the system. If the
temperature reaches a designated high set point, the IC is
shutdown and stops switching.
2
DS929F1
CS1610/11/12/13
2. PIN DESCRIPTION
Boost Zero-current Detect
Rectifier Voltage Sense
Voltage Clamp Current Source
Source Ground
Source Switch
No Connect
No Connect
Boost Peak Current
BSTAUX
IAC
CLAMP
SGND
SOURCE
NC
NC
IPK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BSTOUT
FBAUX
VDD
GD
GND
FBSENSE
eOTP
FBGAIN
Boost Output Voltage Sense
Second Stage Zero-current Detect
IC Supply Voltage
Gate Driver
Ground
Second Stage Current Sense
External Overtemperature Protection
Second Stage Gain
16-lead SOICN
Figure 2. CS1610/11/12/13 Pin Assignments
Pin Name
BSTAUX
Pin #
I/O
Description
Boost Zero-current Detect
— Boost Inductor demagnetization sensing input for
zero-current detection (ZCD) information. The pin is connected to the PFC boost
inductor auxiliary winding through an external resistor divider.
Rectifier Voltage Sense
— A current proportional to the rectified line voltage is fed
into this pin. The current is measured with an A/D converter.
Voltage Clamp Current Source
— Connect to a voltage clamp circuit on the output
of the boost stage.
Source Ground
— Common reference current return for the SOURCE pin.
Source Switch
— Connected to the source of the boost stage external high-voltage
FET.
No Connect
— Connect this pin to VDD using a pull-up resistor.
No Connect
— Connect this pin to VDD using a pull-up resistor.
Boost Peak Current
— Connect a resistor to this pin to set the peak current of the
boost circuit.
Second Stage Gain
— Connect a resistor to this pin to set the switching frequency
gain for the second stage.
External Overtemperature Protection
— Connect an external NTC thermistor to
this pin, allowing the internal A/D converter to sample the change to NTC resistance.
Second Stage Current Sense
— The current flowing in the second stage FET is
sensed across a resistor. The resulting voltage is applied to this pin and digitized for
use by the second stage computational logic to determine the FET's duty cycle.
Ground
— Common reference. Current return for both the input signal portion of the
IC and the gate driver.
Gate Driver
— Gate drive for the second stage power FET.
IC Supply Voltage
— Connect a storage capacitor to this pin to serve as a reservoir for
operating current for the device, including the gate drive current to the power transistor.
Second Stage Zero-current Detect
— Second stage inductor sensing input. The
pin is connected to the second stage inductor’s auxiliary winding through an external
resistor divider.
Boost Output Voltage Sense
— A current proportional to the boost output is fed
into this pin. The current is measured with an A/D converter.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN
IN
OUT
PWR
IN
IN
IN
IN
IN
IN
IN
PWR
OUT
PWR
IN
IN
IAC
CLAMP
SGND
SOURCE
NC
NC
IPK
FBGAIN
eOTP
FBSENSE
GND
GD
VDD
FBAUX
BSTOUT
DS929F1
3
CS1610/11/12/13
3. CHARACTERISTICS AND SPECIFICATIONS
3.1 Electrical Characteristics
Typical
characteristics conditions:
• T
A
= 25 °C, V
DD
= 12V, GND = 0 V
• All voltages are measured with respect to GND.
• Unless otherwise specified, all currents are positive
when flowing into the IC.
Minimum/Maximum
characteristics conditions:
• T
J
= -40°C to +125 °C, V
DD
= 11V to 17V, GND = 0 V
Parameter
VDD Supply Voltage
Operating Range
Turn-on Threshold Voltage
Turn-off Threshold Voltage (UVLO)
Zener Voltage
VDD Supply Current
Startup Supply Current
Operating Supply Current
Reference
Reference Current
CS1610/12
CS1611/13
Boost
Maximum Switching Frequency
Clamp Current
Dimmer Attach Peak Current
CS1610/12
CS1611/13
Boost Zero-Current Detect
BSTZCD Threshold
BSTZCD Blanking
ZCD Sink Current
BSTAUX Upper Voltage
Boost Protection
Boost Overvoltage Protection (BOP)
CS1610/12
CS1611/13
Clamp Turn On
CS1610/12
CS1611/13
Second Stage Zero-Current Detect
FBZCD Threshold
FBZCD Blanking
ZCD Sink Current
FBAUX Upper Voltage
(Note 2)
(Note 2)
(Note 5)
(Note 1)
Condition
After Turn-on
V
DD
Increasing
V
DD
Decreasing
I
DD
= 20mA
V
DD
<V
ST(th)
C
L
= 0.25nF, f
sw
70
kHz
Symbol
V
DD
V
ST(th)
V
STP(th)
V
Z
I
ST
Min
11
-
-
18.5
-
-
Typ
-
8.5
7.5
-
-
4.5
Max
17
-
-
19.8
200
-
Unit
V
V
V
V
A
mA
V
BST
= 200 V
V
BST
= 400 V
I
ref
-
-
-
-
-
-
133
133
-
-3.7
590
508
200
3.5
-
V
DD
+0.6
-
-
200
-
-
-
-
-
-
-
A
A
kHz
mA
mA
mA
mV
s
mA
V
f
BST(Max)
I
CLAMP
108
V
line
132
207 V
line
253
V
BSTZCD(th)
t
BSTZCB
I
ZCD
I
ZCD
= 1 mA
-
-
-2
-
108
V
line
132
207 V
line
253
108
V
line
132
207 V
line
253
V
BOP(th)
-
-
-
-
162
148
147
143
200
2
-
V
DD
+0.6
-
-
-
-
-
-
-
-
A
A
A
A
mV
s
mA
V
V
FBZCD(th)
t
FBZCB
I
ZCD
I
ZCD
= 1mA
-
-
-2
-
4
CS1610/11/12/13
CS1610/11/12/13
Parameter
Second Stage Current Sense
Overcurrent Protection Threshold
Sense Resistor Short Threshold
Peak Control Threshold
Leading-edge Blanking
Delay to Output
Second Stage Pulse Width Modulator
Minimum On Time
Maximum On Time
Minimum Switching Frequency
Maximum Switching Frequency
Second Stage Gate Driver
Output Source Resistance
Output Sink Resistance
Rise Time
Fall Time
Second Stage Protection
Overcurrent Protection (OCP)
Overvoltage Protection (OVP)
Open Loop Protection (OLP)
Pull-up Current Source – Maximum
Conductance Accuracy
Conductance Offset
Current Source Voltage Threshold
Internal Overtemperature Protection (iOTP)
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Notes:
1.
2.
3.
4.
5.
(Note 4)
(Note 4)
(Note 3)
(Note 3)
(Note 5)
(Note 5)
Condition
Symbol
V
OCP(th)
V
OLP(th)
V
Pk_Max(th)
t
LEB
Min
-
-
-
-
-
-
-
Typ
1.69
200
1.4
550
-
0.55
8.8
625
200
24
11
-
-
1.69
1.25
200
80
-
±250
1.25
135
14
Max
-
-
-
-
100
-
-
-
-
-
-
30
20
-
-
-
-
±5
-
-
-
-
Unit
V
mV
V
ns
ns
s
s
Hz
kHz
ns
ns
V
V
mV
A
nS
V
ºC
ºC
t
FB(Min)
t
FB(Max)
V
DD
= 13V
V
DD
= 13V
C
L
= 0.25nF
C
L
= 0.25nF
-
-
-
-
-
-
Z
OUT
Z
OUT
V
OCP(th)
V
OVP(th)
V
OLP(th)
I
CONNECT
-
-
-
-
-
-
External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain
V
CONNECT(th)
T
SD
T
SD(Hy)
-
-
-
The CS1610/11/12/13 has an internal shunt regulator that limits the voltage on the VDD pin. V
Z
, the shunt regulation voltage, is
defined in the
VDD Supply Voltage
section on
page 4.
External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased
does not exceed specification.
The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4M
resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.
Specifications are guaranteed by design and are characterized and correlated using statistical process methods.
For test purposes, load capacitance (C
L
) is 0.25nF and is connected as shown in the following diagram.
V
DD
VDD
GD
+15V
TP
Buffer
S
1
R
1
C
L
0.25nF
R
2
-15V
GD OUT
S
2
R
3
CS
GND
DS929F1
5
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