NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ZL2102
3A Digital-DC Synchronous Step-Down DC/DC
Converter
ZL2103
The ZL2103 is an innovative power conversion and
management IC that combines an integrated synchronous
step-down DC/DC converter with key power management
functions in a small package, resulting in a flexible and
integrated solution.
The ZL2103 can provide an output voltage from 0.54V to 5.5V
(with margin) from an input voltage between 4.5V and 14V.
Internal low r
DS(ON)
synchronous power MOSFETs enable the
ZL2103 to deliver continuous loads up to 3A with high
efficiency. An internal Schottky bootstrap diode reduces
discrete component count. The ZL2103 also supports phase
spreading to reduce system input capacitance.
Power management features such as digital soft-start delay
and ramp, sequencing, tracking, and margining can be
configured by simple pin-strapping or through an on-chip serial
port. The ZL2103 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for interoperability between other Zilker Labs devices.
Features
• Integrated MOSFET switches
• 3A continuous output current
• ±1% output voltage accuracy
•
Snapshot™
parametric capture
• I
2
C/SMBus interface, PMBus compatible
• Internal non-volatile memory (NVM)
Applications*
(see page 27)
• Telecom, Networking, Storage equipment
• Test and Measurement equipment
• Industrial control equipment
• 5V and 12V distributed power systems
Related Literature
• See
AN2010
“Thermal and Layout Guidelines for Digital-
DC™ Products”
• See
AN2033
“Zilker Labs PMBus Command Set-DDC
Products PMBus Command Set”
• See
AN2035
“Compensation Using CompZL™”
100
V
OUT
= 3.3V
90
80
70
60
50
40
0.0
V
IN
= 12V
f
SW
= 200kHz
L = 6µH
0.5
1.0
1.5
I
OUT
(A)
2.0
2.5
3.0
EFFICIENCY (%)
FIGURE 1. ZL2103 EFFICIENCY
May 3, 2011
FN6966.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ZL2103
Typical Application Circuit
The following application circuit represents a typical
implementation of the ZL2103. For PMBus operation, it is
recommended to tie the enable pin (EN) to SGND.
C
RA
4.7µF
F.B.
‡
C
DD
2.2µF
DDC Bus
ENABLE
†
C
25
10µF
C
R
4.7µF
V
IN
12V
C
IN
100µF
DDC 34
V2P5 33
VRA 32
MGN 35
VR 31
EN 36
VDDS 30
VDDP 29
VDDP 28
PGOOD
1 PG
2 DGND
3 SYNC
4 VSET
5 SA
VDDP 27
BST 26
SW 25
C
B
47nF
ZL2103
SW 24
SW 23
SW 22
SW 21
SW 20
L
OUT
2.2µH
I C/
SMBus
††
2
6 SCL
7 SDA
8 SALRT
15 PGND
9 FC
14 SGND
17 PGND
16 PGND
V
OUT
3.3V
PGND 19
18 PGND
C
OUT
150µF
ePAD
(SGND)
10 CFG
Notes:
‡
Ferrite bead is optional for input noise suppression.
†
The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
connected. The 10 k default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise
time. Please refer to the Digital-DC Bus section for more details.
††
The I
2
C/SMBus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
connected. Please refer to the I
2
C/SMBus specifications for more details.
FIGURE 2. 12V TO 3.3V/3A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP)
Block Diagram
V
IN
VDDS
V2P5
VDDP
BST
VRA
VR
EN
PG
MGN
VSET
CFG
SS
VTRK
DDC
SA
2.5V
LDO
5V
LDO
11 SS
13 VSEN
12 VTRK
7V
LDO
PWM
Control
&
Drivers
Power
Mgmt
DDC Bus
SMBus
SALRT
SW
V
OUT
VSEN
NVM
PGND
SDA
SCL
FIGURE 3. BLOCK DIAGRAM
2
SYNC
FN6966.5
May 3, 2011
ZL2103
Pin Configuration
ZL2103
(36 LD QFN)
TOP VIEW
EN
MGN
DDC
V2P5
VRA
VR
VDDS
VDDP
VDDP
34
33
32
36
35
31
30
29
PG
DGND
SYNC
VSET
SA
SCL
SDA
SALRT
FC
28
1
2
3
4
5
6
7
8
9
12
13
14
10
11
15
16
17
18
27
ZL2103
36-Pin QFN
6 x 6 mm
26
25
24
23
22
21
20
19
Exposed Paddle
Connect to SGND
VDDP
BST
SW
SW
SW
SW
SW
SW
PGND
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16, 17,
18, 19
20, 21, 22,
23, 24, 25
26
27, 28, 29
30
LABEL
PG
DGND
SYNC
VSET
SA
SCL
SDA
SALRT
FC
CFG
SS
VTRK
VSEN
SGND
PGND
SW
BST
VDDP
VDDS
TYPE
(Note 1)
O
PWR
I/O, M
(Note 2)
I, M
I, M
I/O
I/O
O
I, M
I, M
I, M
I
I
PWR
PWR
I/O
PWR
PWR
PWR
DESCRIPTION
Power-good. This pin transitions high 100ms after output voltage stabilizes within regulation band.
Selectable open drain or push-pull output. Factory default is open drain.
Digital ground. Common return for digital signals. Connect to low impedance ground plane.
Clock synchronization pin. Used to set switching frequency of internal clock or for synchronization to
external frequency reference.
Output voltage select pin. Used to set V
OUT
set-point and V
OUT
max.
Serial address select pin. Used to assign unique SMBus address to each IC.
Serial clock. Connect to external host interface.
Serial data. Connect to external host interface.
Serial alert. Connect to external host interface if desired.
Loop compensation select pin. Used to set loop compensation.
Configuration pin. Used to control the SYNC pin, sequencing and enable tracking.
Soft-start pin. Used to set the ramp delay and ramp time, sets UVLO and configure tracking.
Track sense pin. Used to track an external voltage source.
Output voltage positive feedback sensing pin.
Common return for analog signals. Connect to low impedance ground plane.
Power ground. Common return for internal switching MOSFETs. Connect to low impedance ground plane.
Switching node (level-shift common).
Bootstrap voltage for level-shift driver (referenced to SW).
Bias supply voltage for internal switching MOSFETs (return is PGND).
IC supply voltage (return is SGND).
3
CFG
SS
VTRK
VSEN
SGND
PGND
PGND
PGND
PGND
FIGURE 4.
FN6966.5
May 3, 2011
ZL2103
Pin Descriptions
(Continued)
PIN
31
32
33
34
35
36
ePad
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pins. Please refer to Section “Multi-mode Pins” on page 12.
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
LABEL
VR
VRA
V2P5
DDC
MGN
EN
SGND
TYPE
(Note 1)
PWR
PWR
PWR
I/O
I
I
PWR
DESCRIPTION
Regulated bias from internal 7V low-dropout regulator (return is PGND). Decouple with a 4.7µF capacitor to
PGND.
Regulated bias from internal 5V low-dropout regulator for internal analog circuitry (return is SGND).
Decouple with a 4.7µF capacitor to SGND.
Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry (return is DGND).
Decouple with a 10µF capacitor.
Digital-DC Bus (open drain). Interoperability between Zilker Labs devices.
Margin pin. Used to enable margining of the output voltage.
Enable pin. Used to enable the device (active high).
Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane.
Ordering Information
PART NUMBER
(Notes 4, 5)
ZL2103ALAF
ZL2103ALAFT (Note 3)
ZL2103ALAFTK (Note 3)
ZL2103EVAL1Z
NOTES:
3. Please refer to
TB347
for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for
ZL2103.
For more information on MSL please see techbrief
TB363.
PART
MARKING
2103
2103
2103
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
36 Ld 6mmx6mm QFN
36 Ld 6mmx6mm QFN
36 Ld 6mmx6mm QFN
PKG.
DWG. #
L36.6x6C
L36.6x6C
L36.6x6C
4
FN6966.5
May 3, 2011
ZL2103
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ZL2103 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
High-side Driver Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Power-good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Component Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Current Sensing and Current Limit Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
I
2
C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
I
2
C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Output Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fault Spreading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Monitoring via I
2
C/SMBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
FN6966.5
May 3, 2011
京公网安备 11010802033920号
EEWORLD
