LFE2M50E-5FN900C datasheet, PDF

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LFE2M50E-5FN900C: DescriptionFPGA - Field Programmable Gate Array 48K LUTs 410 I/O Memory DSP 1.2V 5SPD; CategoryProgrammable logic devices Programmable logic; File Size16MB，771 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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LFE2M50E-5FN900C Overview

FPGA - Field Programmable Gate Array 48K LUTs 410 I/O Memory DSP 1.2V 5SPD

LFE2M50E-5FN900C Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	BGA
package instruction	BGA, BGA900,30X30,40
Contacts	900
Reach Compliance Code	compliant
ECCN code	EAR99
maximum clock frequency	311 MHz
Combined latency of CLB-Max	0.358 ns
JESD-30 code	S-PBGA-B900
JESD-609 code	e1
length	31 mm
Humidity sensitivity level	3
Number of entries	410
Number of logical units	50000
Output times	410
Number of terminals	900
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA900,30X30,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	250
power supply	1.2 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.6 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	31 mm

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LatticeECP2/M Family Handbook

HB1003 Version 05.3, February 2012

LatticeECP2/M Family Handbook

Table of Contents

February 2012

Section I. LatticeECP2/M Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ........................................................................................................................................................ 2-3

Slice .......................................................................................................................................................... 2-3

Modes of Operation................................................................................................................................... 2-5

Routing............................................................................................................................................................... 2-6

sysCLOCK Phase Locked Loops (GPLL/SPLL) ................................................................................................ 2-6

General Purpose PLL (GPLL) ................................................................................................................... 2-6

Standard PLL (SPLL) ................................................................................................................................ 2-7

Delay Locked Loops (DLL)................................................................................................................................. 2-8

DLLDELA Delay Block .............................................................................................................................. 2-9

PLL/DLL Cascading .................................................................................................................................. 2-9

GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) .................................................. 2-10

Clock Dividers .................................................................................................................................................. 2-10

Clock Distribution Network ............................................................................................................................... 2-11

Primary Clock Sources............................................................................................................................ 2-11

Secondary Clock/Control Sources .......................................................................................................... 2-13

Edge Clock Sources................................................................................................................................ 2-14

Primary Clock Routing ............................................................................................................................ 2-15

Dynamic Clock Select (DCS) .................................................................................................................. 2-15

Secondary Clock/Control Routing ........................................................................................................... 2-15

Slice Clock Selection............................................................................................................................... 2-17

Edge Clock Routing ................................................................................................................................ 2-18

sysMEM Memory ............................................................................................................................................. 2-19

sysMEM Memory Block........................................................................................................................... 2-19

Bus Size Matching .................................................................................................................................. 2-19

RAM Initialization and ROM Operation ................................................................................................... 2-19

Memory Cascading ................................................................................................................................. 2-19

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-19

Memory Core Reset ................................................................................................................................ 2-20

EBR Asynchronous Reset....................................................................................................................... 2-20

sysDSP™ Block ............................................................................................................................................... 2-21

sysDSP Block Approach Compared to General DSP ............................................................................. 2-21

sysDSP Block Capabilities ...................................................................................................................... 2-21

MULT sysDSP Element .......................................................................................................................... 2-23

MAC sysDSP Element ............................................................................................................................ 2-24

MULTADDSUB sysDSP Element ........................................................................................................... 2-25

MULTADDSUBSUM sysDSP Element ................................................................................................... 2-26

Clock, Clock Enable and Reset Resources ............................................................................................ 2-26

Signed and Unsigned with Different Widths............................................................................................ 2-27

OVERFLOW Flag from MAC .................................................................................................................. 2-27

IPexpress™............................................................................................................................................. 2-28

Optimized DSP Functions ................................................................................................................................ 2-28

Resources Available in the LatticeECP2/M Family ................................................................................. 2-28

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2/M DSP Performance .......................................................................................................... 2-29

Programmable I/O Cells (PIC) ......................................................................................................................... 2-29

PIO ................................................................................................................................................................... 2-31

Input Register Block ................................................................................................................................ 2-31

Output Register Block ............................................................................................................................. 2-33

Tristate Register Block ............................................................................................................................ 2-35

Control Logic Block ................................................................................................................................. 2-35

DDR Memory Support...................................................................................................................................... 2-35

Left and Right Edges............................................................................................................................... 2-35

Bottom Edge ........................................................................................................................................... 2-35

Top Edge................................................................................................................................................. 2-36

DLL Calibrated DQS Delay Block ........................................................................................................... 2-37

Polarity Control Logic .............................................................................................................................. 2-39

DQSXFER............................................................................................................................................... 2-40

sysI/O Buffer .................................................................................................................................................... 2-40

sysI/O Buffer Banks ................................................................................................................................ 2-40

Typical sysI/O I/O Behavior During Power-up......................................................................................... 2-43

Supported sysI/O Standards ................................................................................................................... 2-43

Hot Socketing.......................................................................................................................................... 2-45

SERDES and PCS (Physical Coding Sublayer)............................................................................................... 2-46

SERDES Block........................................................................................................................................ 2-46

PCS......................................................................................................................................................... 2-47

SCI (SERDES Client Interface) Bus........................................................................................................ 2-47

IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-48

Device Configuration........................................................................................................................................ 2-48

Soft Error Detect (SED) Support ............................................................................................................. 2-48

External Resistor..................................................................................................................................... 2-49

On-Chip Oscillator................................................................................................................................... 2-49

Density Shifting ................................................................................................................................................ 2-49

DC and Switching Characteristics

Absolute Maximum Ratings

, ,

............................................................................................................................. 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

ESD Performance .............................................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

LatticeECP2 Supply Current (Standby).............................................................................................................. 3-4

LatticeECP2M Supply Current (Standby)........................................................................................................... 3-5

LatticeECP2 Initialization Supply Current .......................................................................................................... 3-6

LatticeECP2M Initialization Supply Current ....................................................................................................... 3-7

SERDES Power Supply Requirements (LatticeECP2M Family Only) ............................................................... 3-8

SERDES Power (LatticeECP2M Family Only)................................................................................................... 3-8

sysI/O Recommended Operating Conditions..................................................................................................... 3-9

sysI/O Single-Ended DC Electrical Characteristics.......................................................................................... 3-10

sysI/O Differential Electrical Characteristics .................................................................................................... 3-11

LVDS....................................................................................................................................................... 3-11

Differential HSTL and SSTL.................................................................................................................... 3-11

LVDS25E ................................................................................................................................................ 3-12

LVCMOS33D .......................................................................................................................................... 3-12

BLVDS .................................................................................................................................................... 3-13

LVPECL .................................................................................................................................................. 3-14

RSDS ...................................................................................................................................................... 3-15

MLVDS.................................................................................................................................................... 3-16

Typical Building Block Function Performance.................................................................................................. 3-17

Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-17

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

Register-to-Register Performance .......................................................................................................... 3-17

Derating Timing Tables .................................................................................................................................... 3-18

LatticeECP2/M External Switching Characteristics.......................................................................................... 3-19

LatticeECP2/M Internal Switching Characteristics ........................................................................................... 3-28

Timing Diagrams .............................................................................................................................................. 3-30

LatticeECP2/M Family Timing Adders ............................................................................................................. 3-32

sysCLOCK GPLL Timing ................................................................................................................................. 3-35

sysCLOCK SPLL Timing.................................................................................................................................. 3-36

DLL Timing....................................................................................................................................................... 3-37

SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) ............................................................ 3-38

SERDES High Speed Data Receiver (LatticeECP2M Family Only) ................................................................ 3-41

Input Data Jitter Tolerance...................................................................................................................... 3-41

SERDES External Reference Clock (LatticeECP2M Family Only) ......................................................... 3-43

SERDES Power-Down/Power-Up Specification .............................................................................................. 3-43

PCI Express Electrical and Timing Characteristics .......................................................................................... 3-44

AC and DC Characteristics ..................................................................................................................... 3-44

LatticeECP2/M sysCONFIG Port Timing Specifications .................................................................................. 3-46

JTAG Port Timing Specifications ..................................................................................................................... 3-50

Switching Test Conditions................................................................................................................................ 3-51

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-4

LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 .......................................................................... 4-5

LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 ........................................................................ 4-7

LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 ........................................................................ 4-9

LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 ............................................................... 4-11

LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100............................................ 4-13

Available Device Resources by Package, LatticeECP2................................................................................... 4-15

Available Device Resources by Package, LatticeECP2M................................................................................ 4-15

LatticeECP2 Power Supply and NC................................................................................................................. 4-16

LatticeECP2 Power Supply and NC (Cont.)..................................................................................................... 4-17

LatticeECP2M Power Supply and NC.............................................................................................................. 4-18

LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-19

LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-21

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP ........................................................... 4-22

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP......................................................... 4-26

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA .......................................................... 4-31

LFE2-20E/SE Logic Signal Connections: 256 fpBGA ...................................................................................... 4-39

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-47

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-60

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-73

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-91

LFE2-70E/SE Logic Signal Connections: 900 fpBGA .................................................................................... 4-109

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA ................................................ 4-134

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA .................................................. 4-141

LFE2M50E/SE Logic Signal Connections: 484 fpBGA .................................................................................. 4-153

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA .................................................. 4-167

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA .................................................. 4-184

LFE2M100E/SE Logic Signal Connections: 900 fpBGA ................................................................................ 4-206

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA .............................................. 4-231

Ordering Information

LatticeECP2 Part Number Description............................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

LatticeECP2 Standard Series Devices, Conventional Packaging............................................................. 5-2

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2 Standard Series Devices, Lead-Free Packaging .......................................................................... 5-5

LatticeECP2 S-Series Devices, Conventional Packaging......................................................................... 5-8

LatticeECP2 S-Series Devices, Lead-Free Packaging ........................................................................... 5-11

LatticeECP2M Part Number Description.......................................................................................................... 5-14

Ordering Information ........................................................................................................................................ 5-14

LatticeECP2M Standard Series Devices, Conventional Packaging........................................................ 5-15

LatticeECP2M Standard Series Devices, Lead-Free Packaging ............................................................ 5-18

LatticeECP2M S-Series Devices, Lead-Free Packaging ........................................................................ 5-23

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

LatticeECP2/M Family Data Sheet Revision History

Revision History ................................................................................................................................................. 7-1

Section II. LatticeECP2/M Family Technical Notes

LatticeECP2M SERDES/PCS Usage Guide

Introduction to PCS ............................................................................................................................................ 8-1

Features ............................................................................................................................................................. 8-1

Supported Standards ......................................................................................................................................... 8-2

Architecture Overview ........................................................................................................................................ 8-2

PCS Quad ................................................................................................................................................. 8-2

PCS Quad and Channels.......................................................................................................................... 8-3

Per Channel PCS/FPGA Interface Ports................................................................................................... 8-4

Locating a PCS Quad ............................................................................................................................... 8-4

Detailed Channel Block Diagram .............................................................................................................. 8-4

SCI (SERDES Client Interface) Bus.......................................................................................................... 8-7

Using This Technical Note ........................................................................................................................ 8-7

SERDES/PCS .................................................................................................................................................... 8-7

I/O Definitions............................................................................................................................................ 8-9

SERDES/PCS Functional Description ............................................................................................................. 8-12

SERDES ................................................................................................................................................. 8-12

Reference Clock Usage .......................................................................................................................... 8-13

Transmit Data.......................................................................................................................................... 8-16

Receive Data........................................................................................................................................... 8-16

Configuration GUIs........................................................................................................................................... 8-27

Configuration File Description ................................................................................................................. 8-38

LatticeECP2M PCS in Gigabit Ethernet Mode ................................................................................................. 8-39

Gigabit Ethernet (1000BASE-X) Idle Insert............................................................................................. 8-39

Gigabit Ethernet Idle Insert and ff_correct_disp_ch[3:0] Signal Usage................................................... 8-39

LatticeECP2M PCS in PCI Express Mode ....................................................................................................... 8-39

PCS Loopback Modes ..................................................................................................................................... 8-41

Serial Loopback Mode ............................................................................................................................ 8-41

SERDES Parallel Loopback Mode.......................................................................................................... 8-41

PCS Parallel Loopback Mode ................................................................................................................. 8-41

FPGA Interface Clocks Usage ......................................................................................................................... 8-42

2-to-1 Gearing ......................................................................................................................................... 8-44

SERDES/PCS Block Latency........................................................................................................................... 8-49

SERDES Client Interface (SCI)........................................................................................................................ 8-50

Interrupts and Status............................................................................................................................... 8-52

SERDES Client Interface Application Example....................................................................................... 8-53

Dynamic Configuration of SERDES/PCS Quad...................................................................................... 8-54

SERDES Debug Capabilities .................................................................................................................. 8-54

Control Boxes and Buttons, Status Boxes and the Text Window ........................................................... 8-56

Other Design Considerations ........................................................................................................................... 8-56

LatticeECP2M-35 vs. All Other LatticeECP2M Devices.......................................................................... 8-56

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