DS1742
Y2KC Nonvolatile Timekeeping RAM
FEATURES
Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM; These Registers are
Resident in the Eight Top RAM Locations
Century Byte Register
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the year 2100
Battery Voltage Level Indicator Flag
Power-Fail Write Protection Allows for ±10%
V
CC
Power Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness until
Power is Applied for the First Time
Standard JEDEC Bytewide 2k x 8 Static
RAM Pinout
Quartz Accuracy ±1 Minute a Month at
+25°C, Factory Calibrated
Underwriters Laboratories (UL) Recognized
VOLTAGE (V)
5.0
5.0
5.0
3.3
3.3
PIN CONFIGURATION
TOP VIEW
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
24
2
23
DS1742
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
13
12
V
CC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
ENCAPSULATED DIP
ORDERING INFORMATION
PART
DS1742-85+
DS1742-100+
DS1742-100IND+
DS1742W-120+
DS1742W-150+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
TOP MARK**
DS1742-85+
DS1742-100+
DS1742-100IND+
DS1742W-120+
DS1742W-150+
+Denotes
a lead(Pb)-free/RoHS-compliant device.
**The top mark will include a “+” on lead(Pb)-free devices.
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19-6715; Rev 6/13
DS1742
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
19
22
23
9
10
11
13
14
15
16
17
12
18
20
21
24
3B
NAME
A7
A6
A5
A4
A3
A2
A1
A0
A10
A9
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
CE
OE
WE
V
CC
FUNCTION
Address Input
Data Input/Output
Ground
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
Power-Supply Input
DESCRIPTION
The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and
2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished
with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in
the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day,
hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month
and leap year are made automatically.
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1742 also
contains its own power-fail circuitry, which deselects the device when the V
CC
supply is in an
out-of-tolerance condition. This feature prevents loss of data from unpredictable system
operation brought on by low V
CC
as errant access and update cycles are avoided.
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DS1742
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data,
internal updates to the DS1742 clock registers should be halted before clock data is read to
prevent reading of data in transition. However, halting the internal clock register updating
process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit,
bit 6 of the century register, see Table 2. As long as a 1 remains in that position, updating is
halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was
current at the moment the halt command was issued. However, the internal clock registers of
the double-buffered system continue to update so that the clock accuracy is not affected by the
access of data. All of the DS1742 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500µs to ensure the external
registers will be updated.
Figure 1. DS1742 BLOCK DIAGRAM
Table 1. TRUTH TABLE
V
CC
CE
V
IH
V
IL
V
CC
> V
PF
V
IL
V
IL
V
SO
< V
CC
< V
PF
X
V
CC
< V
SO
< V
PF
X
0B
OE
WE
X
X
V
IL
V
IH
X
X
X
V
IL
V
IH
V
IH
X
X
MODE
Deselect
Write
Read
Read
Deselect
Deselect
1B
DQ
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
2B
32B
POWER
Standby
Active
Active
Active
CMOS Standby
Data Retention Mode
3B
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DS1742
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts
updates to the DS1742 registers. The user can subsequently load correct date and time values
into all eight registers, followed by a write cycle of 00h to the Control register to clear the W bit
and transfer those new settings into the clock, allowing timekeeping operations to resume from
the new set point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1
halts updates to the DS1742 registers. The user can subsequently read the date and time
values from the eight registers without those contents possibly changing during those I/O
operations. A subsequent write cycle of 00h to the Control register to clear the R bit allows
timekeeping operations to resume from the previous set-point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified
by a write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a
write cycle to Control if the W bit is being cleared to 0 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by
a write cycle to Control if the R bit is being cleared to 0 in that write operation.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be
turned off to minimize current drain from the battery. The
OSC
bit is the MSB (bit 7) of the
seconds registers, see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit
is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512
Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency
as long as conditions for access remain valid (i.e.,
CE
low,
OE
low,
WE
high, and address for
seconds register remain valid and stable).
CLOCK ACCURACY
The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. Dallas
Semiconductor calibrates the RTC at the factory using nonvolatile tuning elements. The
DS1742 does not require additional calibration. For this reason, methods of field clock
calibration are not available and not necessary. Clock accuracy is also affected by the electrical
environment and caution should be taken to place the RTC in the lowest level EMI section of
the PCB layout. For additional information, refer to Application Note 58.
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DS1742
Table 2. REGISTER MAP
ADDRES
S
B
7
B
6
B
5
7FF
10 Year
7FE
7FD
7FC
7FB
7FA
7F9
7F8
OSC = STOP BIT
W = WRITE BIT
DATA
B
4
B
3
B
2
B
1
Year
Month
B
0
FUNCTION
42B
43B
RANGE
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–39
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
X
X
BF
X
X
OSC
X
X
FT
X
W
R
10
Month
10 Date
X
X
10 Hour
10 Minutes
10 Seconds
10 Century
X
X
Date
Day
Hour
Minutes
Seconds
Century
R = READ BIT
X = SEE NOTE BELOW
FT = FREQUENCY TEST
BF = BATTERY FLAG
Note:
All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock operation.
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Talking
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