EEWORLDEEWORLDEEWORLD

Part Number

Search

ES29DS400D-12RTG

Description
32Mbit(4M x 8/2M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory
File Size594KB,59 Pages
ManufacturerEXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
Download Datasheet View All

ES29DS400D-12RTG Overview

32Mbit(4M x 8/2M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory

E S I
I
ES
Excel Semiconductor inc.
ES29LV320D
32Mbit(4M x 8/2M x 16)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
GENERAL FEATURES
• Single power supply operation
- 2.7V -3.6V for read, program and erase operations
• Minimum 100,000 program/erase cycles per sector
• 20 Year data retention at 125
o
C
SOFTWARE FEATURES
• Sector Structure
- 8Kbyte x 8 boot sectors
- 64Kbyte x 63 sectors
- 256byte security sector
• Top or Bottom boot block
- ES29LV320DT for Top boot block device
- ES29LV320DB for Bottom boot block device
• A 256 bytes of extra sector for security code
- Factory lockable
- Customer lockable
• Package Options
- 48-pin TSOP
- Pb-free packages
- All Pb-free products are RoHS-Compliant
• Low Vcc write inhibit
• Manufactured on 0.18um process technology
• Compatible with JEDEC standards
- Pinout and software compatible with single-power
supply flash standard
Erase Suspend / Erase Resume
Data# poll and toggle for Program/erase status
CFI ( Common Flash Interface) supported
Unlock Bypass program
Autoselect mode
Auto-sleep mode after t
ACC
+ 30ns
HARDWARE FEATURES
• Hardware reset input pin ( RESET#)
- Provides a hardware reset to device
- Any internal device operation is terminated and the
device returns to read mode by the reset
• Ready/Busy# output pin ( RY/BY#)
- Provides a program or erase operational status
about whether it is finished for read or still being
progressed
• WP#/ACC input pin
- Two outermost boot sectors are protected when
WP# is set to low, regardless of sector protection
- Program speed is accelerated by raising WP#/ACC
to a high voltage (12V)
• Sector protection / unprotection ( RESET# , A9 )
- Hardware method of locking a sector to prevent
any program or erase operation within that sector
- Two methods are provided :
- In-system method by RESET# pin
- A9 high-voltage method for PROM programmers
• Temporary Sector Unprotection ( RESET# )
- Allows temporary unprotection of previously
protected sectors to change data in-system
DEVICE PERFORMANCE
• Read access time
- 90ns/120n for normal Vcc range ( 2.7V - 3.6V )
- 80ns for regulated Vcc range ( 3.0V - 3.6V )
• Program and erase time
- Program time : 9us/byte, 11us/word ( typical )
- Accelerated program time : 8us/word ( typical )
- Sector erase time : 0.7sec/sector ( typical )
• Power consumption (typical values)
- 200nA in standby or automatic sleep mode
- 10 mA active read current at 5 MHz
- 15mA active write current during program or erase
ES29LV320D
1
Rev. 2D Jan 5, 2006
Britain's first eco-friendly bus hits the road using human feces as fuel
[i=s]This post was last edited by wanzsxit on 2014-11-20 12:47[/i] [align=center]The UK's first eco-bus that uses human feces as fuel has hit the road. Developers say this environmentally friendly bus...
wanzsxit Talking
How to allocate multiple interrupts
My recent program needs to use multiple interrupts, timer interrupts, serial port transceiver interrupts, but how can I avoid conflicts when using these multiple interrupts?...
atom1212 Microcontroller MCU
The most amazing voltage regulated output in history
Today I made a circuit: The transformer has a positive and negative AC 12V input, and a rectifier bridge is connected. If you calculate, you will get a DC voltage of about 30V; Then connect three volt...
零下12度半 Power technology
Evaluation: STM32F769I-DISCO connected to Gizwits Cloud to realize IoT development remote control and other functions
Evaluation: STM32F769I-DISCO connected to Gizwits Cloud to realize IoT development remote control and other functionsAbstract: This article mainly describes how to use STM32F769I-DISCO to connect to G...
z3512641347 MCU
How does CPLD achieve frequency addition?
Recently, I tested a mature motherboard. The input signal of CPLD was 60M/8192=7.324kHZ, the clock of CPLD was 60MHZ, and the test output was 7.5M+7.324k. In CPLD, the main clock was divided by 8 and ...
qiang6091 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 347  1036  963  186  542  7  21  20  4  11 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号