EN25P40-75GCP datasheet, PDF - EEWORLD Datasheet

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EN25P40-75GCP: Description4 Mbit Uniform Sector, Serial Flash Memory; File Size431KB，31 Pages; ManufacturerEon; Websitehttp://www.essi.com.tw/

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EN25P40-75GCP Overview

4 Mbit Uniform Sector, Serial Flash Memory

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EN25P40

4 Mbit Uniform Sector, Serial Flash Memory

FEATURES

•

Single power supply operation

- Full voltage range: 2.7-3.6 volt

•

4 Mbit Serial Flash

- 4 M-bit/512 K-byte/2048 pages

- 256 bytes per programmable page

•

High performance

- 75MHz clock rate

•

Low power consumption

- 5 mA typical active current

- 1

μA

typical power down current

•

Uniform Sector Architecture:

- Eight 64-Kbyte sectors

•

Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

•

High performance program/erase speed

Byte program time: 7µs typical

Page program time: 1.5ms typical

Sector erase time: 800 ms typical

Chip erase time: 5 Seconds typical

•

Minimum 100K endurance cycle

•

Package Options

8 pins SOP 150mil body width

8 pins SOP 200mil body width

8 contact VDFN

All Pb-free packages are RoHS compliant

•

Commercial and industrial temperature

Range

GENERAL DESCRIPTION

The EN25P40 is a 4M-bit (512K-byte) Serial Flash memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to

256 bytes at a time, using the Page Program instruction.

The EN25P40 is designed to allow either single Sector at a time or full chip erase operation. The

EN25P40 can be configured to protect part of the memory as the software protected mode. The device

can sustain a minimum of 100K program/erase cycles on each sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. D, Issue Date: 2006/12/25

EN25P40

SIGNAL DESCRIPTION

Serial Data Input (DI)

The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be

serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)

input pin.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from

(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device

is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the

devices power consumption will be at standby levels unless an internal erase, program or status

consumption will increase to active levels and instructions can be written to and data read from the

device. After power-up, CS# must transition from high to low before a new instruction will be

accepted.

Hold (HOLD#)

The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought

low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will

be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same

SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used

in conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status

Table 1. PIN Names

Symbol

CLK

CS#

WP#

HOLD#

Vcc

Vss

Pin Name

Serial Clock Input

Serial Data Input

Serial Data Output

Chip Enable

Write Protect

Hold Input

Supply Voltage (2.7-3.6V)

Ground

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. D, Issue Date: 2006/12/25

EN25P40

OPERATING FEATURES

SPI Modes

The EN25P40 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0

(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure

3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not

being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK

signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.

Data output on the DO pin is clocked out on the falling edge of SCK.

Figure 3. SPI Modes

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a

Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal

Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at

a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of

memory.

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the

bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time,

using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)

instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be

preceded by a Write Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE)

can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress

(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it

to establish when the previous Write cycle, Program cycle or Erase cycle is complete.

Active Power, Stand-by Power and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select

(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles

have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power

mode. The device consumption drops to

CC1

The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode

(DP) instruction) is executed. The device consumption drops further to

CC2

. The device remains in this

mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID

(RDI) instruction) is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as

an extra software protection mechanism, when the device is not in active use, to protect the device from

inadvertent Write, Program or Erase instructions.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. D, Issue Date: 2006/12/25

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