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EDE1104ABSE-5C-E

Description
1G bits DDR2 SDRAM
Categorystorage    storage   
File Size609KB,82 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Environmental Compliance
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EDE1104ABSE-5C-E Overview

1G bits DDR2 SDRAM

EDE1104ABSE-5C-E Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerELPIDA
Parts packaging codeBGA
package instructionTFBGA, BGA68,9X19,32
Contacts68
Reach Compliance Codeunknow
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Maximum access time0.5 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)267 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B68
JESD-609 codee1
length18.2 mm
memory density1073741824 bi
Memory IC TypeDDR DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals68
word count268435456 words
character code256000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize256MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA68,9X19,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length4,8
Maximum slew rate0.3 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature50
width10.2 mm
DATA SHEET
1G bits DDR2 SDRAM
EDE1104ABSE (256M words
×
4 bits)
EDE1108ABSE (128M words
×
8 bits)
EDE1116ABSE (64M words
×
16 bits)
Specifications
Density: 1G bits
Organization
32M words
×
4 bits
×
8 banks (EDE1104ABSE)
16M words
×
8 bits
×
8 banks (EDE1108ABSE)
8M words
×
16 bits
×
8 banks (EDE1116ABSE)
Package
68-ball FBGA (EDE1104/1108ABSE)
92-ball FBGA (EDE1116ABSE)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
Data rate
800Mbps/667Mbps/533Mbps/400Mbps (max.)
1KB page size (EDE1104/1108ABSE)
Row address: A0 to A13
Column address: A0 to A9, A11 (EDE1104ABSE)
A0 to A9 (EDE1108ABSE)
2KB page size (EDE1116ABSE)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at 0°C
TC
≤ +85°C
3.9μs at
+85°C <
TC
≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Document No. E0852E50 (Ver. 5.0)
Date Published February 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2005-2007
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