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74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
April 1988
Revised October 2000
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a
3-STATE serial output. In the Serial-Out mode, the data
recirculates in the shift register. By means of a separate
clock, the contents of the shift register are transferred to
the storage register for parallel outputting. The contents of
the storage register can also be parallel loaded back into
the shift register. A HIGH signal on the Chip Select input
prevents both shifting and parallel transfer. The storage
register may be cleared via STMR.
Features
s
Serial-to-parallel converter
s
16-bit serial I/O shift register
s
16-bit parallel-out storage register
s
Recirculating serial shifting
s
Recirculating parallel transfer
s
Common serial data I/O pin
s
Slim 24 lead package
Ordering Code:
Order Number
74F673ASC
74F673APC
74F673ASPC
Package Number
M24B
N24A
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS009585
www.fairchildsemi.com
74F673A
Unit Loading/Fan Out
Pin Names
CS
SHCP
STMR
STCP
R/W
SI/O
Q
0
–Q
15
Description
Chip Select Input (Active LOW)
Shift Clock Pulse Input (Active Falling Edge)
Store Master Reset Input (Active LOW)
Store Clock Pulse Input
Read/Write Input
Serial Data Input or
3-STATE Serial Output
Parallel Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
3.5/1.0
150/40
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
70
µ
A/
−
0.6 mA
−
3 mA/24 mA
−
1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of four modes, as
indicated in the Shift Register Operations Table. A HIGH
signal on the Chip Select (CS) input prevents clocking and
forces the Serial Input/Output (SI/O) 3-STATE buffer into
the high impedance state. During serial shift-out opera-
tions, the SI/O buffer is active (i.e., enabled) and the output
data is also recirculated back into the shift register. When
parallel loading the shift register from the storage register,
serial shifting is inhibited.
The storage register has an asynchronous master reset
(STMR) input that overrides all other inputs and forces the
Q
0
–Q
15
outputs LOW. The storage register is in the Hold
mode when either CS or the Read/Write (R/W) input is
HIGH. With CS and R/W both LOW, the storage register is
parallel loaded from the shift register.
Shift Register Operations Table
Control Inputs
CS R/W SHCP STCP
H
L
L
X
L
H
X
X
X
L
SI/O
Operating Mode
Status
High Z
Data In
Hold
Serial Load
Storage Register Operations Table
Control Inputs
STMR
L
H
H
H
CS
X
H
X
L
R/W
X
X
H
L
STCP
X
X
Operating
Mode
Reset; Outputs LOW
Hold
Hold
Parallel Load
L
H
Data Out Serial Output
with Recirculation
H
Active
Parallel Load;
No Shifting
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Transition
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
X
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2
74F673A
Block Diagram
3
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74F673A
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
BVIT
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
Output Leakage
Current
Output Leakage
Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
114
114
−60
10% V
CC
10% V
CC
2.5
2.4
2.7
2.7
0.5
0.5
20
100
1.0
−0.6
70
−650
−150
250
500
172
172
V
µA
µA
mA
mA
µA
µA
mA
µA
µA
mA
mA
Min
Max
Max
Max
Max
Max
Max
Max
Max
0.0V
Max
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA (Non I/O pins)
I
OH
= −1
mA (Q
n
, SI/O)
I
OH
= −3
mA (SI/O)
I
OH
= −1
mA (Q
n
, SI/O)
I
OH
= −3
mA (SI/O)
I
OL
=
20 mA (Q
n
)
I
OL
=
24 mA (SI/O)
V
IN
=
2.7V (Non I/O pins)
V
IN
=
7.0V (Non I/O pins)
V
IN
=
5.5V (SI/O)
V
IN
=
0.5V
V
OUT
=
2.7V (SI/O)
V
OUT
=
0.5V (SI/O)
V
OUT
=
0V
V
OUT
=
V
CC
V
OUT
=
5.25V
V
O
=
HIGH
V
O
=
LOW
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