ZL40241LDG1 datasheet, PDF - EEWORLD Datasheet

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ZL40241LDG1: DescriptionClock Driver; Categorylogic; File Size647KB，23 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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Clock Driver

ZL40241LDG1 Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	HVQCCN, LCC32,.2SQ,20
Reach Compliance Code	compliant
Factory Lead Time	8 weeks
Other features	ALSO OPERATE AT 3.3V SUPPLY; SEATED HT-CALCULATED
series	4000/14000/40000
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32
length	5 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TRAY
Maximum supply current (ICC)	20 mA
propagation delay (tpd)	2.77 ns
Same Edge Skew-Max（tskwd）	0.027 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	5 mm
minfmax	200 MHz
Base Number Matches	1

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Data Sheet

ZL40241

Ten LVCMOS Output Low Additive Jitter Fanout Buffer

Features

•

3 to 1 input Multiplexer: Two inputs accept any

differential (LVPECL, HCSL, LVDS, SSTL, CML,

LVCMOS) or a single ended signal and the third

input accepts a crystal or a single ended signal

•

Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs

•

Supports frequencies from 0 to 200MHz

•

Supports crystals from 8MHz to 60MHz

•

Ultra-low additive jitter: 17fs (12kHz to 20MHz)

•

Ultra-low noise floor of -170dBc/Hz

•

Supports 2.5V or 3.3V power supplies

•

Output to output skew of 30ps (typical)

•

Input to output delay of 2ns (typical)

Applications

•

General purpose clock distribution

Low jitter clock trees

Logic translation

Clock and data signal restoration

Wired and Wireless communications

High performance microprocessor clock distribution

Medical Imaging

Test equipment

ZL40241LDG1

ZL40241LDF1

Ordering Information

32 Pin QFN

32 pin QFN

Trays

Tape and Reel

Package size: 5 x 5 mm

-40



C to +85



-40



C to +85



ZL40241

OUT0

Synchronous OE

OUT1

SEL0

SEL1

IN0_p

IN0_n

OUT2

OUT3

IN1_p

IN1_n

OUT4

XOUT

OUT5

XIN

OUT6

OUT7

OUT8

OUT9

Figure 1. Functional Block Diagram

October 2018

ZL40241

Data Sheet

ZL40241

Table of Contents

Features ..................................................................................................................................... 1

Table of Contents ...................................................................................................................... 2

Pin Diagram ............................................................................................................................... 5

Pin Descriptions ......................................................................................................................... 6

Functional Description ............................................................................................................... 8

Clock Inputs ............................................................................................................................... 8

Clock Outputs .......................................................................................................................... 11

Crystal Oscillator Input ............................................................................................................. 11

Termination of unused inputs and outputs .............................................................................. 12

Power Consumption ................................................................................................................ 13

Power Supply Filtering ............................................................................................................. 15

Device Control ......................................................................................................................... 15

AC and DC Electrical Characteristics ...................................................................................... 16

Absolute Maximum Ratings ..................................................................................................... 16

Recommended Operating Conditions ..................................................................................... 16

Package Outline ...................................................................................................................... 21

Revision History ....................................................................................................................... 22

October 2018

ZL40241

Data Sheet

ZL40241

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Functional Block Diagram ........................................................................................................................................... 1

Pin Diagram ................................................................................................................................................................ 5

Input driven by a single ended output ........................................................................................................................ 8

Input driven by DC coupled LVPEVCL output .............................................................................................................. 8

Input driven by DC coupled LVPEVCL output (alternative termination) ...................................................................... 9

Input driven by AC coupled LVPECL output ................................................................................................................. 9

Input driven by HCSL output ....................................................................................................................................... 9

Input driven by LVDS output ..................................................................................................................................... 10

Input driven by AC coupled LVDS .............................................................................................................................. 10

Input driven by an SSTL output ................................................................................................................................. 10

Termination for 3.3V LVPECL outputs ....................................................................................................................... 11

Crystal Oscillator Circuit............................................................................................................................................ 11

Phase Noise Plot with 25MHz Crystal ....................................................................................................................... 12

Device power consumption per output for V

= V

DDO

= 3.465V ............................................................................... 13

Device power consumption per output for V

= V

DDO

= 2.625V ............................................................................... 14

Dynamic supply current per output for different output supply voltages ................................................................ 14

Power Supply Filtering .............................................................................................................................................. 15

October 2018

ZL40241

Data Sheet

ZL40241

List of Tables

Table 1 · Pin Descriptions ............................................................................................................................................................................... 6

Table 2 · Absolute Maximum Ratings* ......................................................................................................................................................... 16

Table 3 · Recommended Operating Conditions* .......................................................................................................................................... 16

Table 4 · Current consumption ..................................................................................................................................................................... 16

Table 5 · Input Characteristics* .................................................................................................................................................................... 17

Table 6 · Crystal Oscillator Characteristics* ................................................................................................................................................. 17

Table 7 · LVCMOS Output Characteristics* .................................................................................................................................................. 18

Table 8 · LVCMOS Output Additive Jitter and Phase Noise* ......................................................................................................................... 19

Table 9 · LVCMOS Output Jitter Phase Noise with 25MHz XTAL*................................................................................................................. 20

Table 10 · 5x5mm QFN Package Thermal Properties ................................................................................................................................... 20

October 2018

ZL40241

ZL40241LDG1 Related Products

	ZL40241LDG1	ZL40241LDF1
Description	Clock Driver	Clock Driver
Maker	Microchip	Microchip
package instruction	HVQCCN, LCC32,.2SQ,20	QFN-32
Reach Compliance Code	compliant	compli
Factory Lead Time	8 weeks	8 weeks
Other features	ALSO OPERATE AT 3.3V SUPPLY; SEATED HT-CALCULATED	ALSO OPERATE AT 3.3V SUPPLY; SEATED HT-CALCULATED
series	4000/14000/40000	4000/14000/40000
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32	S-XQCC-N32
length	5 mm	5 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	1	1
Number of terminals	32	32
Actual output times	10	10
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20	LCC32,.2SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TRAY	TR
Maximum supply current (ICC)	20 mA	20 mA
propagation delay (tpd)	2.77 ns	2.77 ns
Same Edge Skew-Max（tskwd）	0.027 ns	0.027 ns
Maximum seat height	1 mm	1 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
width	5 mm	5 mm
minfmax	200 MHz	200 MHz

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