Intel
®
LXT9785 and Intel
®
LXT9785E
Advanced 8-Port 10/100 Mbps PHY
Transceivers
Datasheet
The Intel
®
LXT9785 and Intel
®
LXT9785E are 8-port Fast Ethernet PHY Transceivers
supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices
provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and
Reduced Media Independent Interface (RMII) for switching and other independent port
applications. The LXT9785 and LXT9785E are identical except for the IP telephony features
included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785
that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5
cable. The system uses the information collected by the LXT97985E to apply power if the DTE
at the far end requires power over the cable, such as an IP telephone.
Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled
Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps
(10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports
100 Mbps (100BASE-FX) Ethernet over fiber-optic media.
The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices
support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a
single 2.5 V power supply.
Applications
Enterprise switches
IP telephony switches
Storage Area Networks
Multi-port Network Interface Cards (NICs)
Product Features
Eight IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters.
100BASE-FX fiber-optic capability on all
ports.
2.5 V operation.
Low power consumption; 250 mW per port
typical.
Multiple RMII or SMII/SS-SMII ports for
independent PHY port operation.
Auto MDI/MDIX crossover capability.
Proprietary Optimal Signal Processing™
architecture improves SNR by 3 dB over
ideal analog filters.
Optimized for dual-high stacked RJ-45
applications.
MDIO sectionalization into 2x4 or 1x8
configurations.
Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability.
Robust baseline wander correction.
Configurable through the MDIO port or
external control pins.
JTAG boundary scan.
208-pin PQFP: LXT9785HC,
LXT9785EHC, LXT9785HE.
241-ball BGA: LXT9785BC,
LXT9785EBC.
196-ball BGA: LXT9785MBC
DTE detection for remote powering
applications (LXT9785E only).
Extended temperature operation of -40
o
C to
+85
o
C (LXT9785HE).
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
LXT9785 and Intel
®
LXT9785E may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
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Copyright © 2003, Intel Corporation
2
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
Contents
1.0
Introduction..................................................................................................................................
18
1.1
1.2
2.0
3.0
What You Will Find in This Document ................................................................................ 18
Related Documents ............................................................................................................ 18
Block Diagram
............................................................................................................................. 19
Pin/Ball Assignments and Signal Descriptions
........................................................................ 20
3.1
PQFP Pin Assignments ...................................................................................................... 20
3.1.1 PQFP Pin Assignments – RMII Configuration ....................................................... 21
3.1.2 PQFP Pin Assignments – SMII Configuration........................................................ 26
3.1.3 PQFP Pin Assignments – SS-SMII Configuration.................................................. 31
PQFP Signal Descriptions .................................................................................................. 36
3.2.1 Signal Name Conventions ..................................................................................... 36
3.2.2 PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations.................. 36
BGA23 Ball Assignments.................................................................................................... 51
3.3.1 RMII BGA23 Ball List ............................................................................................. 52
3.3.2 SMII BGA23 Ball List ............................................................................................. 62
3.3.3 SS-SMII BGA23 Ball List ....................................................................................... 72
BGA23 Signal Descriptions ................................................................................................ 82
3.4.1 Signal Name Conventions ..................................................................................... 82
3.4.2 Signal Descriptions – RMII, SMII, and SS-SMII Configurations............................. 82
BGA15 Ball Assignments.................................................................................................... 98
3.5.1 BGA15 Ball List...................................................................................................... 99
BGA15 Signal Descriptions ..............................................................................................109
3.6.1 Signal Name Conventions ...................................................................................109
3.6.2 Signal Descriptions – SMII and SS-SMII Configurations .....................................109
Introduction .......................................................................................................................116
4.1.1 OSP™ Architecture .............................................................................................116
4.1.2 Comprehensive Functionality ..............................................................................117
4.1.2.1 Sectionalization ....................................................................................117
Interface Descriptions .......................................................................................................117
4.2.1 10/100 Network Interface.....................................................................................117
4.2.1.1 Twisted-Pair Interface ..........................................................................118
4.2.1.2 MDI Crossover (MDIX).........................................................................119
4.2.1.3 Fiber Interface......................................................................................119
Media Independent Interface (MII) Interfaces...................................................................119
4.3.1 Global MII Mode Select .......................................................................................119
4.3.2 Internal Loopback ................................................................................................120
4.3.3 RMII Data Interface..............................................................................................120
4.3.4 Serial Media Independent Interface (SMII) and Source Synchronous-
Serial Media Independent Interface (SS-SMII) ....................................................121
4.3.4.1 SMII Interface.......................................................................................121
4.3.4.2 Source Synchronous-Serial Media Independent Interface ..................121
4.3.5 Configuration Management Interface ..................................................................121
4.3.6 MII Isolate ............................................................................................................121
3.2
3.3
3.4
3.5
3.6
4.0
Functional Description..............................................................................................................116
4.1
4.2
4.3
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
3
Contents
4.4
4.5
4.6
4.7
4.8
4.9
4.3.7 MDIO Management Interface .............................................................................. 121
4.3.8 MII Sectionalization.............................................................................................. 123
4.3.9 MII Interrupts........................................................................................................ 123
4.3.10 Global Hardware Control Interface ...................................................................... 124
4.3.11 FIFO Initial Fill Values.......................................................................................... 124
Operating Requirements................................................................................................... 125
4.4.1 Power Requirements ........................................................................................... 125
4.4.2 Clock/SYNC Requirements ................................................................................. 125
4.4.2.1 Reference Clock .................................................................................. 125
4.4.2.2 TxCLK Signal (SS-SMII only)............................................................... 125
4.4.2.3 TxSYNC Signal (SMII/SS-SMII)........................................................... 125
4.4.2.4 RxSYNC Signal (SS-SMII only) ........................................................... 125
4.4.2.5 RxCLK Signal (SS-SMII only) .............................................................. 126
Initialization ....................................................................................................................... 126
4.5.1 MDIO Control Mode............................................................................................. 126
4.5.2 Hardware Control Mode....................................................................................... 126
4.5.3 Power-Down Mode .............................................................................................. 127
4.5.3.1 Global (Hardware) Power Down .......................................................... 128
4.5.3.2 Port (Software) Power Down ............................................................... 128
4.5.4 Reset ................................................................................................................... 128
4.5.5 Hardware Configuration Settings......................................................................... 129
Link Establishment............................................................................................................ 129
4.6.1 Auto-Negotiation .................................................................................................. 129
4.6.1.1 Base Page Exchange .......................................................................... 129
4.6.1.2 Manual Next Page Exchange .............................................................. 130
4.6.1.3 Controlling Auto-Negotiation ................................................................ 130
4.6.1.4 Link Criteria.......................................................................................... 130
4.6.1.5 Parallel Detection................................................................................. 131
4.6.1.6 Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode .......................................................... 131
Serial MII Operation.......................................................................................................... 132
4.7.1 SMII Reference Clock.......................................................................................... 135
4.7.2 TxSYNC Pulse (SMII/SS-SMII)............................................................................ 135
4.7.3 Transmit Data Stream.......................................................................................... 135
4.7.3.1 Transmit Enable................................................................................... 135
4.7.3.2 Transmit Error ...................................................................................... 135
4.7.4 Receive Data Stream........................................................................................... 136
4.7.4.1 Carrier Sense....................................................................................... 136
4.7.4.2 Receive Data Valid .............................................................................. 136
4.7.4.3 Receive Error ....................................................................................... 136
4.7.4.4 Receive Status Encoding..................................................................... 136
4.7.5 Collision ............................................................................................................... 136
4.7.6 Source Synchronous-Serial Media Independent Interface .................................. 137
RMII Operation ................................................................................................................. 141
4.8.1 RMII Reference Clock.......................................................................................... 141
4.8.2 Transmit Enable................................................................................................... 142
4.8.3 Carrier Sense & Data Valid.................................................................................. 142
4.8.4 Receive Error....................................................................................................... 142
4.8.5 Out-of-Band Signaling ......................................................................................... 142
4.8.6 4B/5B Coding Operations .................................................................................... 142
100 Mbps Operation ......................................................................................................... 145
4
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Contents
4.9.1
4.9.2
4.10
4.11
4.12
4.13
4.14
100BASE-X Network Operations .........................................................................145
100BASE-X Protocol Sublayer Operations..........................................................145
4.9.2.1 PCS Sublayer ......................................................................................145
4.9.3 PMA Sublayer ......................................................................................................147
4.9.3.1 Link ......................................................................................................148
4.9.3.2 Link Failure Override............................................................................148
4.9.3.3 Carrier Sense/Data Valid (RMII) ..........................................................148
4.9.3.4 Carrier Sense (SMII) ............................................................................148
4.9.3.5 Receive Data Valid (SMII)....................................................................148
4.9.3.6 Twisted-Pair PMD Sublayer .................................................................149
4.9.3.7 Fiber PMD Sublayer.............................................................................149
10 Mbps Operation ...........................................................................................................150
4.10.1 Preamble Handling ..............................................................................................150
4.10.2 Dribble Bits ..........................................................................................................151
4.10.3 Link Test ..............................................................................................................151
4.10.3.1 Link Failure ..........................................................................................151
4.10.4 Jabber ..................................................................................................................151
DTE Discovery Process ....................................................................................................152
4.11.1 Definitions ............................................................................................................152
4.11.2 Interaction between Processor, MAC, and PHY ..................................................153
4.11.3 Management Interface and Control .....................................................................153
4.11.4 DTE Discovery Process Flow ..............................................................................154
4.11.5 DTE Discovery Behavior......................................................................................155
Monitoring Operations ......................................................................................................157
4.12.1 Monitoring Auto-Negotiation ................................................................................157
4.12.2 Per-Port LED Driver Functions ............................................................................157
4.12.3 Out-of-Band Signaling .........................................................................................158
4.12.4 Boundary Scan Interface .....................................................................................159
4.12.5 State Machine ......................................................................................................159
4.12.6 Instruction Register ..............................................................................................159
4.12.7 Boundary Scan Register ......................................................................................159
Cable Diagnostics Overview .............................................................................................160
4.13.1 Features...............................................................................................................160
4.13.2 Operation .............................................................................................................160
4.13.2.1 Short and Long Cable Testing Requirements ......................................160
4.13.2.2 Precision ..............................................................................................160
4.13.3 Implementation Considerations ...........................................................................161
4.13.4 Basic Implementation ..........................................................................................161
Link Hold-Off Overview .....................................................................................................162
4.14.1 Features...............................................................................................................162
4.14.2 Operation .............................................................................................................163
Design Recommendations................................................................................................164
General Design Guidelines ...............................................................................................164
5.2.1 Power Supply Filtering .........................................................................................164
5.2.2 Power and Ground Plane Layout Considerations................................................165
5.2.2.1 Chassis Ground ...................................................................................165
5.2.3 MII Terminations ..................................................................................................165
5.2.4 Twisted-Pair Interface ..........................................................................................165
5.2.4.1 Magnetic Requirements .......................................................................166
5.0
Application Information
............................................................................................................164
5.1
5.2
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
5
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