Design Idea DI-31
™
DPA-Switch
5 V, 70 W DC-DC
Converter with Synchronous Rectification
Application
DC-DC Converter
Device
DPA426R
Power Output
70 W
Input Voltage
36-75 VDC
Output Voltage
5V
®
Topology
Forward
Design Highlights
•
•
•
•
•
•
Extremely low component count
High efficiency, 90% using synchronous rectification
No current sense resistor or current transformer required
Output overload, open loop and thermal protection
Accurate input under/overvoltage meets ETSI standards
300 kHz switching frequency – optimizes efficiency using Capacitor C9, diodes D1-D2, and inductor L2 form a resonant
simple self-driven synchronous rectification
snubber that recycles leakage and magnetizing energy stored
in T1, and also helps to reset T1. Zener diode VR1 provides
a hard voltage limit and only conducts during output transient
Operation
and overload conditions. Capacitor C12 and Resistor R7
The 70 W converter shown in Figure 1 benefits from many of damp secondary switching spikes and help to reset T1.
the
DPA-Switch
integrated features. In particular, no external
current sense components are required. In a discrete
implementation, an expensive current transformer and a number
Key Design Points
of additional components would increase the cost of this • For nominal undervoltage set point V :
UV
converter significantly.
R1 = (V
UV
- 2.35 V)/50
µA.
V
OV
= (R1
x
135
µA)
+ 2.5 V.
• Locate C10, C11, and R3 close to the U1 CONTROL pin,
R1 programs the input UV/OV thresholds. The tight tolerance
with ground connections returned to SOURCE pin.
of the UV/OV thresholds limits the range of gate drive voltages
C7 1 nF
1.5 kV
+
VIN
36-75 VDC
L1
1
µH
2.5 A
1
applied to MOSFETs Q1 to Q6, eliminating the need for gate
voltage clamp circuitry. The self-driven synchronous
rectification configuration is therefore very simple, with R4
to R6 filtering voltage spikes at the gates of Q1, Q2 and Q3
and D4 preventing the body diodes of Q4, Q5 and Q6 from
conducting.
T1
9,10
R4-R6
10
Ω
Q4-Q6
SI4842DY
L3
3.8
µH
20 A
C13, C14,
C15, C16, C17
100
µF
10 V
(x5)
L4
100 nH
20 A
C18, C19
100
µF
10 V
5 V, 14 A
C20
1
µF
10 V
RTN
D1
ESD1
R1
619 kΩ
6,7
2
D4
Q1-Q3
42CTQ30S
SI4842DY
C12 2.2 nF, 50 V
R7
1
Ω
U2
3
C1, C2
1
µF
100 V
C3, C4,
C5, C6
1
µF
100 V
(x4)
C9
150 pF
200 V
5
4
D
L
CONTROL
CONTROL
L5
D3
2.2 mH
BAV19WS 40 mA
D5
BAV19WS
C8
1
µF
25 V
R13
10 kΩ
D6
BAV19WS
R15
10.0 kΩ
1%
C22
100 nF
R10
5.1
Ω
R14
220
Ω
C21 1
µF
DPA-Switch
C
L2
220
µH
S
U1
DPA426R
R11
150
Ω
U2
PC357N1T
C23
10
µF
10 V
U3
LM431AIM3
X
F
-VIN
VR1
SMBJ
150
D2
ESD1
R3
1.0
Ω
C10
220 nF
R2
6.8 kΩ
1%
C11
68
µF
10 V
R16
10.0 kΩ
1%
PI-3375-121602
Figure 1. DPA426 70 W, 5 V, 14 A DC-DC Converter.
DI-31
www.powerint.com
December 2002
DI-31
• Minimize primary and secondary high current loop areas
to reduce parasitic inductance.
• Optocoupler U2 should have a controlled CTR range of
100 to 200% for optimum loop stability.
• Size transformer reset components to ensure transformer
reset at minimum operating voltage without exceeding
170 V drain voltage at high line. It may be necessary to gap
T1 to offset effect of Q4-Q6 gate capacitance.
• Set Zener VR1 clamp voltage to 150 V to both safely limit
the DRAIN below BV
DSS
and guarantee transformer reset.
• Select number of bias turns to provide 12 V to 14 V at
minimum input voltage and full load.
• Main primary power return should be connected to the
DPA-Switch
tab, not to the SOURCE pin.
• Scale time constant of C9 and L2 to allow C9 to reset
completely during minimum on-time conditions.
• Consult AN-31 for additional design tips and information.
PI-3376-091502
TRANSFORMER PARAMETERS
Core Material
Bobbin
EFD25, 3F3
Gap for
A
LG
= 1100 nH/T
2
EFD25 10 pin
(B&B B-025 or equivalent)
Bias: 5T, 30 AWG
Primary: 6T+ 5T, 4 x 26 AWG
Secondary: 3T, 0.005" Cu foil
Primary (3-2), tape, Bias (4-5), tape,
Secondary (6,7-9,10), tape,
Primary (2-1), tape
Primary: 130
µH ±10%,
Leakge: 10
µH
(max)
3 MHz (minimum)
Winding Details
Winding Order
(Pin Numbers)
Inductance
Primary Resonant
Frequency
Table 1. Transformer Design Parameters.
92
90
OUTPUT INDUCTOR PARAMETERS
Core
Bobbin
Winding Details
EE22, TDK PC40 Material
Gap for
A
LG
of 250 nH/T
2
TDK BE-22-5116
4T, 0.016" Cu foil
4
µH ±
10%
Efficiency (%)
88
86
84
82
80
V
IN
= 36 VDC
V
IN
= 48 VDC
V
IN
= 60 VDC
V
IN
= 72 VDC
Inductance
Table 2. Output Inductor Construction Information.
80
0
20
40
60
Output Power (W)
Figure 2. Efficiency vs. Output Power.
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Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any
license under its patent rights or the rights of others. The products and applications illustrated herein may be covered by one or more U.S.
and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power
Integrations’ patents may be found at www.powerint.com.
The PI Logo,
TOPSwitch
,
TinySwitch
,
LinkSwitch
and
EcoSmart
are registered trademarks of Power Integrations, Inc.
PI Expert
is a trademark of Power Integrations, Inc. ©Copyright 2002, Power Integrations, Inc.
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