2:4, LVDS Output Fanout Buffer, 2.5V
IDT8SLVD1204I
Datasheet
Description
The IDT8SLVD1204I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8SLVD1204I is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVD1204I ideal for those clock
distribution applications demanding well-defined performance and
repeatability.
Two selectable differential inputs and four low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
Four low skew, low additive jitter LVDS output pairs
Two selectable differential clock input pairs
Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
Maximum input clock frequency: 2GHz
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 20ps (maximum)
Propagation delay: 300ps (maximum)
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
10kHz - 20MHz: 95fs (maximum)
Full 2.5V supply voltage
Lead-free (RoHS 6), 16-Lead VFQFPN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
VDD
Pin Assignment
nQ1
nQ0
Q1
12 11 10
Q2 13
Q0
9
8
V
REF
7 nPCLK0
6 PCLK0
5
V
DD
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
Q0
nQ0
nQ2 14
Q3 15
nQ3 16
1
GND
2
SEL
3
PCLK1
4
nPCLK1
GND GND
VDD
Q1
0
nQ1
IDT8SLVD1204I
16 lead VFQFPN
3.0mm x 3.0mm x 0.9mm package body
1.7mm x 1.7mm ePad
NL Package
Top View
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
Q2
1
nQ2
GND GND
VDD
Q3
nQ3
SEL
Pullup/Pulldown
GND
V
REF
Reference
Voltage
Generator
1
©2018 Integrated Device Technology, Inc.
IDT8SLVD1204I January 21, 2018
IDT8SLVD1204I DATASHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
GND
SEL
PCLK1
nPCLK1
V
DD
PCLK0
nPCLK0
V
REF
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Power
Input
Input
Input
Power
Input
Input
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Power supply ground.
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Power supply pin.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Bias voltage reference for the PCLK, nPCLK inputs.
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
Input
SEL
0
1
Open (default)
Operation
PCLK0, nPCLK0 is the selected differential clock input.
PCLK1, nPCLK1 is the selected differential clock input.
Input buffers are disabled and outputs are static.
NOTE: SEL is an asynchronous control.
IDT8SLVD1204I January 21, 2018
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©2018 Integrated Device Technology, Inc.
IDT8SLVD1204I DATASHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
V
REF
current Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±2mA
125°C
-65C to 150C
2000V
1500V
Electrical Characteristics
Table 4A. Power Supply Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
Parameter
Power Supply Voltage
SEL = 0 or 1; f
REF
= 100MHz;
Q0 to Q3 terminated 100 between nQx, Qx
I
DD
Power Supply Current
SEL = 0 or 1; f
REF
= 800MHz;
Q0 to Q3 terminated 100 between nQx, Qx
SEL = 0 or 1; f
REF
= 2GHz;
Q0 to Q3 terminated 100 between nQx, Qx
Test Conditions
Minimum
2.375
Typical
2.5
84
84
84
Maximum
2.625
100
100
100
Units
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
dI3
V
IH
V
IL
I
IH
I
IL
Parameter
Open-Pin Voltage
(Default State)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL
SEL
SEL
SEL
SEL
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Open
0.7 * V
DD
-0.3
Minimum
Typical
V
DD
/ 2
V
DD
+ 0.3
0.2 * V
DD
150
Maximum
Units
V
V
V
µA
µA
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©2018 Integrated Device Technology, Inc.
IDT8SLVD1204I DATASHEET
Table 4C. Differential Input DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High
Current
Input Low
Current
PCLK0, nPCLK1
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0,
nPCLK1
Test Conditions
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
I
REF
= ±1mA
f
REF
< 1.5 GHz
f
REF
> 1.5 GHz
-10
-150
V
DD
– 1.50
0.1
0.2
1.0
V
DD
– 1.35
V
DD
– 1.15
1.5
1.5
V
DD
– 0.6
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
I
IL
V
REF
V
PP
V
CMR
Reference Voltage for Input Bias
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.15
Test Conditions
Minimum
250
Typical
Maximum
450
50
1.45
50
Units
mV
mV
V
mV
IDT8SLVD1204I January 21, 2018
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©2018 Integrated Device Technology, Inc.
IDT8SLVD1204I DATASHEET
AC Electrical Characteristics
Table 5. AC Electrical Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
Parameter
Input
Frequency
Input
Edge Rate
PCLK[0:1],
nPCLK[0:1]
PCLK[0:1],
nPCLK[0:1]
PCLK[0:1], nPCLK[0:1] to any Qx, nQx
for V
PP
= 0.1V or 0.3V
1.5
120
210
300
20
20
f
REF
= 100MHz
15
230
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
t
R
/ t
F
MUX
ISOLATION
Output Rise/ Fall Time
Mux Isolation; NOTE 5
20% to 80%
outputs loaded with 100
f
REF
= 100MHz
40
72
138
92
92
89
65
65
87
64
64
205
135
135
130
95
95
130
95
95
250
Test Conditions
Minimum
Typical
Maximum
2
Units
GHz
V/ns
ps
ps
ps
ps
ps
fs
fs
fs
fs
fs
fs
fs
fs
fs
ps
dB
Propagation Delay;
NOTE 1
Output Skew; NOTE 2, 3
Input Skew; NOTE 3
Pulse Skew
Part-to-Part Skew;
NOTE 3, 4
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
NOTE 5: Qx, nQx outputs measured differentially. See
MUX Isolation diagram
in the
Parameter Measurement Information section.
IDT8SLVD1204I January 21, 2018
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