DS80C390
Dual CAN High-Speed
Microprocessor
GENERAL DESCRIPTION
The DS80C390 is a fast 8051-compatible
microprocessor with dual CAN 2.0B controllers. The
redesigned
processor
core
executes
8051
instructions up to 3X faster than the original for the
same crystal speed. The DS80C390 supports a
maximum crystal speed of 40MHz, resulting in
apparent
execution
speeds
of
100MHz
(approximately 2.5X). An optional internal frequency
multiplier allows the microprocessor to operate at full
speed with a reduced crystal frequency, reducing
EMI. A hardware math accelerator further increases
the speed of 32-bit and 16-bit multiply and divide
operations as well as high-speed shift, normalization,
and accumulate functions.
The
High-Speed Microcontroller User’s Guide
and
High-Speed
Microcontroller User’s Guide: DS80C390 Supplement
must be
used in conjunction with this data sheet.
Download both at:
www.maxim-ic.com/microcontrollers.
FEATURES
80C52 Compatible
High-Speed Architecture
4kB Internal SRAM Usable as Program/
Data/Stack Memory
Enhanced Memory Architecture
Two Full-Function CAN 2.0B Controllers
Two Full-Duplex Hardware Serial Ports
Programmable IrDA Clock
High Integration Controller
16 Interrupt Sources with Six External
Available in 64-Pin LQFP, 68-Pin PLCC
See page 29 for a complete list of features.
ORDERING INFORMATION
PART
DS80C390-QCR
DS80C390-QCR+
DS80C390-QNR
DS80C390-QNR+
DS80C390-FCR
DS80C390-FCR+
DS80C390-FNR
DS80C390-FNR+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
68 PLCC
68 PLCC
68 PLCC
68 PLCC
64 LQFP
64 LQFP
64 LQFP
64 LQFP
APPLICATIONS
Industrial Controls
Factory Automation
Medical Equipment
Agricultural Equipment
Gaming Equipment
Heating, Ventilation, and
Air Conditioning
+Denotes
a lead(Pb)-free/RoHS-compliant device.
PIN CONFIGURATIONS
9
1
61
48
33
TOP VIEW
10
60
49
32
Dallas Semiconductor
DS80C390
Dallas Semiconductor
DS80C390
26
44
64
17
27
43
PLCC
1
16
LQFP
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 050115
DS80C390 Dual CAN High-Speed Microprocessor
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………….-0.3V to (V
CC
+ 0.5V)
Voltage Range on V
CC
Relative to Ground……………………………………………………………………-0.3V to +6.0V
Operating Temperature Range………………………………………………………………………………..-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Soldering Temperature…..……………………………………………………………………..See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 10)
PARAMETER
Supply Voltage
Power-Fail Warning
Minimum Operating Voltage
Supply Current, Active Mode (Note 1)
Supply Current, Idle Mode (Note 2)
Supply Current, Stop Mode (Note 3)
Supply Current, Stop Mode, Bandgap Enabled (Note 3)
Input Low Level
Input High Level
Input High Level for XTAL1, RST
Output Low Voltage for Port 1, 3, 4, 5 at I
OL
= 1.6mA
Output Low Voltage for Port 0, 1, 2, 4, 5,
RD, WR, RSTOL, PSEN,
and ALE at I
OL
= 3.2mA (Note 5)
Output High Voltage for Port 1, 3, 4, 5 at I
OH
= -50µA (Note 4)
Output High Voltage for Port 1, 3, 4, 5 at I
OH
= -1.5mA (Note 6)
Output High Voltage for Port 0, 1, 2, 4, 5,
RD, WR, RSTOL, PSEN,
and ALE at I
OH
= -8mA (Note 5, 7)
Input Low Current for Port 1, 3, 4, 5 at 0.45V (Note 8)
Logic 1 to 0 Transition Current for Port 1, 3, 4, 5 (Note 9)
Input Leakage Current for Port 0 (Input Mode Only)
RST Pulldown Resistance
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
SYMBOL
V
CC
V
PFW
V
RST
I
CC
I
IDLE
I
STOP
I
SPBG
V
IL
V
IH
V
IH2
V
OL1
V
OL2
V
OH1
V
OH2
V
OH3
I
IL
I
T1
I
L
R
RST
MIN
V
RST
4.10
3.85
TYP
5.0
4.38
4.13
80
40
1
150
MAX
5.5
4.60
4.35
150
75
120
350
+0.8
V
CC
+0.5
V
CC
+0.5
0.45
0.45
UNITS
V
V
V
mA
mA
µA
µA
V
V
V
V
V
V
V
V
-0.5
2.0
0.7 x V
CC
2.4
2.4
2.4
-55
-650
+300
170
-300
50
µA
µA
µA
kΩ
Note 7:
Note 8:
Note 9:
Note 10:
Active current measured with 40MHz clock source on XTAL1, V
CC
= RST = 5.5V, all other pins disconnected.
Idle mode current measured with 40MHz clock source on XTAL1, V
CC
= 5.5V, RST =
EA
= V
SS
, all other pins disconnected.
Stop mode current measured with XTAL1 = RST =
EA
= V
SS
, V
CC
= 5.5V, all other pins disconnected.
RST = V
CC
. This condition mimics operation of pins in I/O mode.
Applies to port pins when they are used to address external memory or as CAN interface signals.
This measurement reflects the port during a 0-to-1 transition in I/O mode. During this period a one-shot circuit drives the ports hard
for two clock cycles. If a port 4 or 5 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing
the pin to an I/O mode (by writing to P4CNT) will not enable the 2-cycle strong pullup. During Stop or Idle mode the pins switch to
I/O mode, and so port 2 and port 1 (in nonmultiplexed mode) will not exhibit the 2-cycle strong pullup when entering Stop or Idle
mode.
Port 3 pins 3.6 and 3.7 have a stronger than normal pullup drive for one oscillator period following the transition of either the
RD
or
WR
from a 0-to-1 transition.
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is
set to 1. This is only the current required to
hold
the low level; transitions from 1 to 0 on an I/O pin also have to overcome the
transition current.
Ports 1(in I/O mode), 3, 4, and 5 source transition current when being pulled down externally. It reaches its maximum at
approximately 2V.
Specifications to -40°C are guaranteed by design and not production tested.
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DS80C390 Dual CAN High-Speed Microprocessor
AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)
(Note 10, Note 11)
PARAMETER
Oscillator Frequency
ALE Pulse Width
Port 0 Instruction Address or
CE0--4
-
Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to
PSEN
Low
PSEN
Pulse Width
PSEN
Low to Valid Instruction In
Input Instruction Hold After
PSEN
Input Instruction Float After
PSEN
Port 0 Address to Valid Instruction In
Port 2, 4 Address to Valid Instruction
In
PSEN
Low to Address Float
Note 11:
SYMBOL
1 / t
CLCL
t
LHLL
t
AVLL
t
LLAX1
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV1
t
AVIV2
t
PLAZ
CONDITIONS
External oscillator
External crystal
40MHz
MIN MAX
0
40
1
40
VARIABLE CLOCK
MIN
MAX
0
40
1
40
0.375 t
MCS
-5
0.125 t
MCS
- 5
0.125 t
MCS
- 5
0.625 t
MCS
- 20
0.125 t
MCS
- 5
0.5 t
MCS
- 8
0.5 t
MCS
- 20
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0.25 t
MCS
- 5
0.75 t
MCS
- 22
0.875 t
MCS
- 30
0
0
ns
ns
ns
ns
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value t
MCS
is a function
of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the
Stretch Value
Timing
table. All signals characterized with load capacitance of 80pF except Port 0, ALE,
PSEN, RD,
and
WR
with 100pF.
Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the
parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This
waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of
signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.
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DS80C390 Dual CAN High-Speed Microprocessor
AC SYMBOLS
The DS80C390 uses timing parameters and symbols similar to the original 8051 family. The following list of timing
symbols is provided as an aid to understanding the timing diagrams.
SYMBOL
t
A
C
CE
D
H
L
I
P
Q
R
V
W
X
Z
FUNCTION
Time
Address
Clock
Chip Enable
Input Data
Logic Level High
Logic Level Low
Instruction
PSEN
Output Data
RD
Signal
Valid
WR
Signal
No longer a valid logic level.
Tri-State
Figure 1. Multiplexed External Program Memory Read Cycle
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DS80C390 Dual CAN High-Speed Microprocessor
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12)
PARAMETER
SYMBOL
MIN
0.375 t
MCS
- 5
0.5 t
MCS
- 5
1.5 t
MCS
- 10
0.125 t
MCS
- 5
0.25t
MCS
- 5
1.25 t
MCS
- 10
0.25t
MCS
-5
0.125 t
MCS
- 5
1.25 t
MCS
- 5
0.5 t
MCS
- 6
C
ST
x t
MCS
- 10
0.5 t
MCS
- 6
C
ST
x t
MCS
- 10
0.5 t
MCS
- 20
C
ST
x t
MCS
- 25
0
0.25 t
MCS
- 5
0.5t
MCS
- 5
1.5 t
MCS
- 5
0.625 t
MCS
- 20
(C
ST
+ 0.25) x t
MCS
- 20
(C
ST
+ 1.25) x t
MCS
- 20
0.75 t
MCS
- 26
(4C
ST
+ 0.5) x t
MCS
- 30
(4C
ST
+ 2.5) x t
MCS
- 30
0.75 t
MCS
- 30
(4C
ST
+ 0.5) x t
MCS
- 30
(4C
ST
+ 2.5) x t
MCS
- 30
0.125 t
MCS
+ 10
0.25t
MCS
+ 10
1.25 t
MCS
+ 10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Note 12
MOVX ALE Pulse Width
Port 0 MOVX Address,
CE0--4,
-
PCE0--4
Valid to ALE Low
-
Address Hold After MOVX
Read/Write
RD
Pulse Width
WR
Pulse Width
RD
Low to Valid Data In
Data Hold After Read
Data Float After Read
t
LHLL2
t
AVLL2
t
LLAX2
t
LLAX3
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
STRETCH
VALUES
C
ST
(MD2:0)
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1≤ C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1≤ C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1≤ C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
=0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
C
ST
= 0
1
≤
C
ST
≤
3
4
≤
C
ST
≤
7
ALE Low to Valid Data In
Port 0 Address, Port 4 CE, Port 5
PCE to Valid Data In
Port 2, 4 Address to Valid Data In
t
LLDV
t
AVDV1
t
AVDV2
0.125 t
MCS
- 5
0.25t
MCS
- 5
1.25 t
MCS
- 5
0.25 t
MCS
- 11
0.5t
MCS
- 11
2.5 t
MCS
- 11
0.375 t
MCS
- 11
0.625t
MCS
- 11
2.625 t
MCS
- 11
-8
0.25 t
MCS
- 8
0.5t
MCS
- 10
1.5 t
MCS
- 10
-5
0.25 t
MCS
- 7
1.25 t
MCS
- 7
ALE Low to
RD
or
WR
Low
Port 0 Address, Port 4 CE, Port 5
PCE to
RD
or
WR
Low
Port 2, 4 Address to or
WR
Low
Data Valid to
WR
Transition
Data Hold After
WR
High
RD
Low to Address Float
RD
or
WR
High to ALE, Port 4 CE
or Port 5 PCE High
Note 12:
t
LLWL
t
AVWL1
t
AVWL2
t
QVWX
t
WHQX
t
RLAZ
t
WHLH
+10
0.25 t
MCS
+ 5
1.25 t
MCS
+10
ns
ns
ns
All parameters apply to both commercial and industrial temperature operation. C
ST
is the stretch cycle value determined by the
MD2:0 bits. t
MCS
is a time period shown in the
t
MCS
Time Periods
table. All signals characterized with load capacitance of 80pF
except Port 0, ALE,
PSEN, RD,
and
WR
with 100pF. Interfacing to memory devices with float times over 25ns can cause bus
contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak
latches maintain the previously driven value from the processor on Port 0 until Port 0 is overdriven by external memory; and on Port
1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2, and 4.
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