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A54SX16A-TQG144M

Description
FPGA - Field Programmable Gate Array SXA
Categorysemiconductor    Programmable logic devices   
File Size731KB,109 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
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A54SX16A-TQG144M Overview

FPGA - Field Programmable Gate Array SXA

A54SX16A-TQG144M Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerMicrosemi
Product CategoryFPGA - Field Programmable Gate Array
Shipping RestrictionsThis product may require additional documentation to export from the United States.
RoHSDetails
Number of I/Os113 I/O
Operating Supply Voltage2.5 V
Minimum Operating Temperature- 55 C
Maximum Operating Temperature+ 125 C
Mounting StyleSMD/SMT
Package / CaseTQFP-144
Height1.4 mm
Length20 mm
Width20 mm
Number of Gates24000
Maximum Operating Frequency227 MHz
Moisture SensitiveYes
Factory Pack Quantity60
Supply Voltage - Max2.75 V
Supply Voltage - Min2.25 V
Unit Weight0.046530 oz
v5.3
SX-A Family FPGAs
u e
Leading-Edge Performance
250 MHz System Performance
350 MHz Internal Performance
Specifications
12,000 to 108,000 Available System Gates
Up to 360 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.22
μ
/ 0.25
μ
CMOS Process Technology
Features
Hot-Swap Compliant I/Os
Power-Up/Down Friendly (No Sequencing Required
for Supply Voltages)
66 MHz PCI Compliant
Nonvolatile, Single-Chip Solution
Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
Devices Support Multiple Temperature Grades
Configurable Weak-Resistor Pull-Up or Pull-Down
for I/O at Power-Up
Individual Output Slew Rate Control
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary-Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and
Design Theft
Table 1 •
SX-A Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary Scan Testing
3.3 V / 5 V PCI
Input Set-Up (External)
Speed Grades
2
Temperature Grades
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP
Notes:
1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers.
2. All –3 speed grades have been discontinued.
A54SX08A
8,000
12,000
768
512
256
512
1
130
3
0
Yes
Yes
0 ns
–F, Std, –1, –2
C, I, A, M
208
100, 144
144
A54SX16A
16,000
24,000
1,452
924
528
990
180
3
0
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
100, 144
144, 256
A54SX32A
32,000
48,000
2,880
1,800
1,080
1,980
249
3
0
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
100, 144, 176
329
144, 256, 484
208, 256
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
256, 484
208, 256
February 2007
© 2007 Actel Corporation
i
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