General Description ........................................................................................................................................ 1
Features ...................................................................................................................................................... 1
Absolute Maximum Conditions.................................................................................................................... 3
Normal Operating Conditions...................................................................................................................... 3
Digital I/O Specifications ............................................................................................................................. 3
DC Specifications ........................................................................................................................................ 4
AC Specifications ........................................................................................................................................ 5
Power and Ground Pins ............................................................................................................................ 10
2
I C Registers..................................................................................................................................................11
2
I C Register Mapping .................................................................................................................................11
2
I C Register Definitions ............................................................................................................................. 12
2
I C Slave Interface and Address ............................................................................................................... 14
Data De-skew Feature .............................................................................................................................. 15
Data Latching Modes ................................................................................................................................ 16
2
I C Programming Sequence ..................................................................................................................... 17
Enabling Hot Plug Detection Mode ........................................................................................................... 17
2
Non I C Mode Configuration ..................................................................................................................... 18
TFT Panel Data Mapping.............................................................................................................................. 20
Figure 6. Input Data Setup/Hold Time to IDCK............................................................................................... 7
Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE....................................................................... 7
Figure 8. DE High and Low Times .................................................................................................................. 7
2
Figure 9. I C Data Valid Delay (driving Read Cycle data) ............................................................................... 7
2
Figure 10. I C Byte Read .............................................................................................................................. 14
2
Figure 11. I C Byte Write .............................................................................................................................. 14
Figure 12.
SiI
164 Data De-skew Feature Timing......................................................................................... 15
Figure 13. 12 bit Input Data Latching............................................................................................................ 16
Figure 14. 24 bit Input Data Latching............................................................................................................ 16
2
Figure 15. Non I C Mode Schematic Example ............................................................................................. 18
2
Figure 16. I C Bus Voltage Level-Shifting using Fairchild NDC7002N ......................................................... 23
2
Figure 17. I C Bus Voltage Level Shifting using Philips GTL 2010............................................................... 23
Figure 18. Voltage Regulation using TL431.................................................................................................. 24
Figure 19. Voltage Regulation using LM317 ................................................................................................. 24
Figure 20. Decoupling and Bypass Capacitor Placement ............................................................................ 25
Figure 21. Decoupling and Bypass Schematic ............................................................................................. 25
Figure 22. Series Input Damping Resistors for Driving Source .................................................................... 26
Figure 23. Example of Incorrect Differential Signal Routing ......................................................................... 26
Figure 24. Example of Correct Differential Signal Routing ........................................................................... 27
Figure 25. Differential Trace Routing to DVI Connector(Top Side View) ...................................................... 27
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