GS81314PT18/36GK-133/120/106
260-Pin BGA
Com & Ind Temp
POD I/O
Features
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4Mb x 36 and 8Mb x 18 organizations available
Organized as 16 logical memory banks
1333 MHz maximum operating frequency
1.333 BT/s peak transaction rate (in billions per second)
96 Gb/s peak data bandwidth (in x36 devices)
Common I/O DDR Data Bus
Non-multiplexed SDR Address Bus
One operation - Read or Write - per clock cycle
Certain address/bank restrictions on Read and Write ops
Burst of 2 Read and Write operations
6 cycle Read Latency
On-chip ECC with virtually zero SER
Loopback signal timing training capability
1.25V ~ 1.3V nominal core voltage
1.2V ~ 1.3V POD I/O interface
Configuration registers
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
144Mb SigmaDDR-IVe™
Burst of 2 Multi-Bank ECCRAM™
Clocking and Addressing Schemes
Up to 1333 MHz
1.25V ~ 1.3V V
DD
1.2V ~ 1.3V V
DDQ
The GS81314PT18/36GK SigmaDDR-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
SigmaDDR-IVe™ Family Overview
SigmaDDR-IVe ECCRAMs are the Common I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Parameter Synopsis
Speed Grade
-133
-120
-106
Max Operating Frequency
1333 MHz
1200 MHz
1066 MHz
Read Latency
6 cycles
6 cycles
6 cycles
V
DD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.09 5/2016
1/40
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PT18/36GK-133/120/106
8M x 18 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCH
(CFG)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
DQ17
V
SS
DQ16
V
SS
DQ15
DQ14
V
SS
CQ1
CQ1
V
SS
NU
IO
NU
IO
V
SS
NU
IO
V
SS
NU
IO
V
SS
V
DD
2
NU
IO
NU
IO
V
DDQ
NU
IO
V
DDQ
NU
IO
NU
IO
V
DDQ
NU
IO
V
DDQ
V
SS
DQ13
V
DDQ
DQ12
DQ11
V
DDQ
DQ10
V
DDQ
DQ9
DQINV1
3
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
NU
I
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
NU
I
9
PZT1
PZT0
V
SS
SA20
V
SS
SA18
V
SS
SA16
V
SS
KD0
KD0
V
SS
MCL
V
SS
RST
V
SS
NC
(1152 Mb)
10
NU
I
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
NU
I
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
12
DQINV0
13
V
DD
V
SS
NU
IO
V
SS
NU
IO
V
SS
NU
IO
NU
IO
V
SS
CQ0
CQ0
V
SS
DQ5
DQ6
V
SS
DQ7
V
SS
DQ8
V
SS
V
DD
MRW
NC
(RSVD)
ZQ
MCL
(SIOM)
MCL
V
SS
SA19
V
SS
SA17
V
SS
SA15
V
SS
KD1
KD1
V
SS
PLL
V
SS
MCH
V
SS
NC
(576 Mb)
MCL
SA13
V
DDQ
SA11
V
DD
SA9
V
DDQ
SA7
V
DD
V
DDQ
SA5
V
DDQ
SA3
V
DD
SA1
V
DDQ
SA21
(x18)
DQ0
V
DDQ
DQ1
V
DDQ
DQ2
DQ3
V
DDQ
DQ4
V
DDQ
V
SS
NU
IO
V
DDQ
NU
IO
NU
IO
V
DDQ
NU
IO
V
DDQ
NU
IO
NU
IO
V
DD
NC
(288 Mb)
SA14
V
DDQ
SA12
V
DD
SA10
V
DDQ
SA8
V
DD
V
DDQ
SA6
V
DDQ
SA4
V
DD
SA2
V
DDQ
SA0
(B2)
V
SS
V
DDQ
NU
I
R/W
V
SS
CK
CK
V
SS
LD
MZT
V
DDQ
V
SS
NC
(RSVD)
V
SS
TCK
TDO
V
DD
RCS
NC
(RSVD)
V
SS
TMS
TDI
MCL
NU
MCL
MCL
Notes:
1. Pins 5B, 6B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.09 5/2016
2/40
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PT18/36GK-133/120/106
4M x 36 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCL
(CFG)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
DQ26
V
SS
DQ25
V
SS
DQ24
DQ23
V
SS
CQ1
CQ1
V
SS
DQ30
DQ29
V
SS
DQ28
V
SS
DQ27
V
SS
V
DD
2
DQINV3
3
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
NU
I
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
NU
I
9
PZT1
PZT0
V
SS
SA20
V
SS
SA18
V
SS
SA16
V
SS
KD0
KD0
V
SS
MCL
V
SS
RST
V
SS
NC
(1152 Mb)
10
NU
I
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
NU
I
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
12
DQINV0
13
V
DD
V
SS
DQ9
V
SS
DQ10
V
SS
DQ11
DQ12
V
SS
CQ0
CQ0
V
SS
DQ5
DQ6
V
SS
DQ7
V
SS
DQ8
V
SS
V
DD
MRW
NC
(RSVD)
ZQ
MCL
(SIOM)
DQ35
V
DDQ
DQ34
V
DDQ
DQ33
DQ32
V
DDQ
DQ31
V
DDQ
V
SS
DQ22
V
DDQ
DQ21
DQ20
V
DDQ
DQ19
V
DDQ
DQ18
DQINV2
MCL
V
SS
SA19
V
SS
SA17
V
SS
SA15
V
SS
KD1
KD1
V
SS
PLL
V
SS
MCH
V
SS
NC
(576 Mb)
MCL
SA13
V
DDQ
SA11
V
DD
SA9
V
DDQ
SA7
V
DD
V
DDQ
SA5
V
DDQ
SA3
V
DD
SA1
V
DDQ
NU
I
(x18)
DQ0
V
DDQ
DQ1
V
DDQ
DQ2
DQ3
V
DDQ
DQ4
V
DDQ
V
SS
DQ13
V
DDQ
DQ14
DQ15
V
DDQ
DQ16
V
DDQ
DQ17
DQINV1
V
DD
NC
(288 Mb)
SA14
V
DDQ
SA12
V
DD
SA10
V
DDQ
SA8
V
DD
V
DDQ
SA6
V
DDQ
SA4
V
DD
SA2
V
DDQ
SA0
(B2)
V
SS
V
DDQ
NU
I
R/W
V
SS
CK
CK
V
SS
LD
MZT
V
DDQ
V
SS
NC
(RSVD)
V
SS
TCK
TDO
V
DD
RCS
NC
(RSVD)
V
SS
TMS
TDI
MCL
NU
MCL
MCL
Notes:
1. Pins 5B, 6B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven High.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.09 5/2016
3/40
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PT18/36GK-133/120/106
Pin Description
Symbol
SA[21:0]
Description
Address
— Read or write address is registered on
CK.
Write/Read Data
— Registered on
KD
and
KD
during Write operations; aligned with
CQ
and
CQ
during Read operations.
DQ[17:0] - x18 and x36.
DQ[35:18] - x36 only.
Write/Read Data Inversion
— Registered on
KD
and
KD
(along with write data) during Write operations;
indicate if the associated write data byte is inverted (DQINVx = 1) or not (DQINVx = 0). Aligned with
CQ
and
CQ
(along with read data) during Read operations; indicate if the associated read data byte is inverted
(DQINVx = 1) or not (DQINVx = 0).
DQINV0 - associated with DQ[8:0] in x18 and x36.
DQINV1 - associated with DQ[17:9] in x18 and x36.
DQINV2 - associated with DQ[26:18] in x36 only.
DQINV3 - associated with DQ[35:27] in x36 only.
Note:
Treated as NU I/Os when Data Inversion is disabled.
Read Data Valid
— Driven high one half cycle before valid read data.
Primary Input Clocks
— Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks
— Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch DQ[17:0], DQINV[1:0] in x36, and DQ[8:0], DQINV0 in x18.
KD1, KD1: latch DQ[35:18], DQINV[3:2] in x36, and DQ[17:9], DQINV1 in x18.
Read Data Output Clocks
— Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with DQ[17:0], DQINV[1:0] in x36, and DQ[8:0], DQINV0 in x18.
CQ1, CQ1: align with DQ[35:18], DQINV[3:2] in x36, and DQ[17:9], DQINV1 in x18.
Load Enable
— Registered onCK. See the Clock Truth Table for functionality.
Read / Write Enable
— Registered on
CK.
See the Clock Truth Table for functionality.
Mode Register Write
— Registered onCK. Can be used synchronously or asynchronously to enable Reg-
ister Write Mode. See the State and Clock Truth Tables for functionality.
PLL Enable
— Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Reset
— Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Driver / ODT Impedance Control Resistor Input
— Must be connected to V
SS
through an external resistor
RQ to program driver and ODT impedances.
Current Source Resistor Input
— Must be connected to V
SS
through an external 2K resistor to provide
an accurate current source for the PLL.
Type
Input
DQ[35:0]
I/O
DQINV[3:0]
I/O
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
Output
Input
Input
CQ[1:0],
CQ[1:0]
LD
R/W
MRW
Output
Input
Input
Input
PLL
Input
RST
ZQ
RCS
Input
Input
Input
Rev: 1.09 5/2016
4/40
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PT18/36GK-133/120/106
Symbol
Description
ODT Mode Select
— Sets the default ODT state globally for all input groups during power-up and reset.
Must be tied High or Low.
MZT = 0: disables ODT on all input groups, regardless of PZT[1:0].
MZT = 1: enables ODT on select input groups, as specified by PZT[1:0].
Note:
The ODT state for each input group can be changed at any time via the Configuration Registers.
ODT Configuration Select
— Set the default ODT state for various combinations of input groups during
power-up and reset, when MZT = 1. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Note:
The ODT state for each input group can be changed at any time via the Configuration Registers.
Core Power Supply
I/O Power Supply
Input Reference Voltage
— Input buffer reference voltage.
Ground
JTAG Clock
— Weakly pulled Low internally.
JTAG Mode Select
— Weakly pulled High internally.
JTAG Data Input
— Weakly pulled High internally.
JTAG Data Output
Must Connect High
— May be tied to V
DDQ
directly or via a 1k resistor.
Must Connect Low
— May be tied to V
SS
directly or via a 1k resistor.
No Connect
— There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input
— There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled High internally. They may be left unconnected or tied/driven High. They should not
be tied/driven Low.
Not Used Input/Output
— There is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled High internally. They may be left unconnected or
tied/driven High. They should not be tied/driven Low.
Type
MZT
Input
PZT[1:0]
Input
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
MCH
MCL
NC
—
—
—
—
Input
Input
Input
Output
Input
Input
—
NU
I
Input
NU
IO
I/O
Rev: 1.09 5/2016
5/40
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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