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GS81314PT36GK-120

Description
Static random access memory 1.2/1.25V 4M x 36 144M
Categorysemiconductor    Memory IC    Static random access memory   
File Size273KB,40 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
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GS81314PT36GK-120 Overview

Static random access memory 1.2/1.25V 4M x 36 144M

GS81314PT36GK-120 Parametric

Parameter NameAttribute value
MakerGSI Technology
Product Categorystatic random access memory
storage144 Mbit
organize4 M x 36
maximum clock frequency1.2 GHz
Interface TypeParallel
Supply voltage - max.1.35 V
Supply voltage - min.1.2 V
Supply current—max.2.75 A
Minimum operating temperature0 C
Maximum operating temperature+ 85 C
Installation styleSMD/SMT
Package/boxBGA-260
EncapsulationTray
storage typeDDR-IV
seriesGS81314PT36GK
typeSigmaDDR-IVe B2
Factory packaging quantity10
GS81314PT18/36GK-133/120/106
260-Pin BGA
Com & Ind Temp
POD I/O
Features
4Mb x 36 and 8Mb x 18 organizations available
Organized as 16 logical memory banks
1333 MHz maximum operating frequency
1.333 BT/s peak transaction rate (in billions per second)
96 Gb/s peak data bandwidth (in x36 devices)
Common I/O DDR Data Bus
Non-multiplexed SDR Address Bus
One operation - Read or Write - per clock cycle
Certain address/bank restrictions on Read and Write ops
Burst of 2 Read and Write operations
6 cycle Read Latency
On-chip ECC with virtually zero SER
Loopback signal timing training capability
1.25V ~ 1.3V nominal core voltage
1.2V ~ 1.3V POD I/O interface
Configuration registers
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
144Mb SigmaDDR-IVe™
Burst of 2 Multi-Bank ECCRAM™
Clocking and Addressing Schemes
Up to 1333 MHz
1.25V ~ 1.3V V
DD
1.2V ~ 1.3V V
DDQ
The GS81314PT18/36GK SigmaDDR-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
SigmaDDR-IVe™ Family Overview
SigmaDDR-IVe ECCRAMs are the Common I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Parameter Synopsis
Speed Grade
-133
-120
-106
Max Operating Frequency
1333 MHz
1200 MHz
1066 MHz
Read Latency
6 cycles
6 cycles
6 cycles
V
DD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.09 5/2016
1/40
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81314PT36GK-120 Related Products

GS81314PT36GK-120 GS81314PT18GK-120I GS81314PT18GK-133I GS81314PT18GK-106 GS81314PT36GK-106 GS81314PT18GK-133 GS81314PT36GK-133I GS81314PT36GK-106I GS81314PT18GK-106I
Description Static random access memory 1.2/1.25V 4M x 36 144M SRAM 1.2/1.25V 8M x 18 144M SRAM 1.2/1.25V 8M x 18 144M SRAM 1.2/1.25V 8M x 18 144M SRAM 1.2/1.25V 4M x 36 144M SRAM 1.2/1.25V 8M x 18 144M Static random access memory 1.2/1.25V 4M x 36 144M Static random access memory 1.2/1.25V 4M x 36 144M Static random access memory 1.2/1.25V 8M x 18 144M
Product Category static random access memory SRAM SRAM SRAM SRAM SRAM static random access memory static random access memory static random access memory
Interface Type Parallel Parallel Parallel Parallel Parallel Parallel Parallel Parallel Parallel
Product Attribute - Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value - - -
Manufacturer - GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology - - -
RoHS - Details Details Details Details Details - - -
Memory Size - 144 Mbit 144 Mbit 144 Mbit 144 Mbit 144 Mbit - - -
Organization - 8 M x 18 8 M x 18 8 M x 18 4 M x 36 8 M x 18 - - -
Maximum Clock Frequency - 1.2 GHz 1.333 GHz 1.066 GHz 1.066 GHz 1.333 GHz - - -
Supply Voltage - Max - 1.35 V 1.35 V 1.35 V 1.35 V 1.35 V - - -
Supply Voltage - Min - 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V - - -
Supply Current - Max - 2.15 A 2.35 A 1.9 A 2.4 A 2.35 A - - -
Minimum Operating Temperature - - 40 C - 40 C 0 C 0 C 0 C - - -
Maximum Operating Temperature - + 100 C + 100 C + 85 C + 85 C + 85 C - - -
Mounting Style - SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT - - -
Package / Case - BGA-260 BGA-260 BGA-260 BGA-260 BGA-260 - - -
Packaging - Tray Tray Tray Tray Tray - - -
Memory Type - DDR-IV DDR-IV DDR-IV DDR-IV DDR-IV - - -
Type - SigmaDDR-IVe B2 SigmaDDR-IVe B2 SigmaDDR-IVe B2 SigmaDDR-IVe B2 SigmaDDR-IVe B2 - - -
Moisture Sensitive - Yes Yes Yes Yes Yes - - -
Factory Pack Quantity - 10 10 10 10 10 - - -
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