SI5342A-D08511-GM datasheet, PDF

Datasheet> All Categories > semiconductor> Analog mixed-signal IC> SI5342A-D08511-GM

SI5342A-D08511-GM: DescriptionClock Synthesizer / Jitter Cleaner Low-Jitter, 2-Output, Any Frequency (<1028MHz), Any Output, Jitter Attenuator; Categorysemiconductor Analog mixed-signal IC; File Size1MB，60 Pages; ManufacturerSilicon Laboratories

Download Datasheet Parametric View All

SI5342A-D08511-GM Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	SI5342A-D08511-GM	-	-	View	Buy Now

SI5342A-D08511-GM Overview

Clock Synthesizer / Jitter Cleaner Low-Jitter, 2-Output, Any Frequency (<1028MHz), Any Output, Jitter Attenuator

SI5342A-D08511-GM Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Clock Synthesizer / Jitter Cleaner

Preview

Download Datasheet

View All

Si5345/44/42 Rev D Data Sheet

10-Channel, Any-Frequency, Any-Output Jitter Attenuator/

Clock Multiplier

These jitter attenuating clock multipliers combine fourth-generation DSPLL

™

and

MultiSynth

™

technologies to enable any-frequency clock generation and jitter attenu-

ation for applications requiring the highest level of jitter performance. These devices

are programmable via a serial interface with in-circuit programmable non-volatile

memory (NVM) so they always power up with a known frequency configuration. They

support free-run, synchronous, and holdover modes of operation, and offer both au-

tomatic and manual input clock switching. The loop filter is fully integrated on-chip,

eliminating the risk of noise coupling associated with discrete solutions. Furthermore,

the jitter attenuation bandwidth is digitally programmable, providing jitter perform-

ance optimization at the application level. Programming the Si5345/44/42 is easy

with Silicon Labs’

ClockBuilder Pro

™

software. Factory preprogrammed devices are

also available.

Applications:

• OTN muxponders and transponders

• 10/40/100 G networking line cards

• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)

• Carrier Ethernet switches

• SONET/SDH line cards

• Broadcast video

• Test and measurement

• ITU-T G.8262 (SyncE) compliant

KEY FEATURES

• Generates any combination of output

frequencies from any input frequency

• Ultra-low jitter of 90 fs rms

• External Crystal: 25 to 54 MHz

• Input frequency range

• Differential: 8 kHz to 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range

• Differential: 100 Hz to 1028 MHz

• LVCMOS: 100 Hz to 250 MHz

• Meets G.8262 EEC Option 1, 2 (SyncE)

• Highly configurable outputs compatible with

LVDS, LVPECL, LVCMOS, CML, and HCSL

with programmable signal amplitude

• Si5345: 4 input, 10 output, 64-QFN 9×9 mm

• Si5344: 4 input, 4 output, 44-QFN 7×7 mm

• Si5342: 4 input, 2 output, 44-QFN 7×7 mm

OSC

IN0

4 Input

Clocks

IN1

IN2

÷INT

Si5342

MultiSynth

DSPLL

MultiSynth

÷INT

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Si5345

OUT8

OUT9

Si5344

Up to 10

Output Clocks

IN3/FB_IN

Status Flags

I2C / SPI

Status Monitor

Control

NVM

÷INT

silabs.com

| Smart. Connected. Energy-friendly.

Rev. 1.1

Si5345/44/42 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional in-

put dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is

controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which

determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth

dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the

MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency.

3.1 Frequency Configuration

The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory.

The combination of fractional input dividers (P

), fractional frequency multiplication (M

), fractional output MultiSynth division

), and integer output division (R

) allows the generation of virtually any output frequency on any of the outputs. All divider values

for a specific frequency plan are easily determined using the ClockBuilder Pro utility.

3.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

tings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always

remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.

3.3 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting

a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-

ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The

DSPLL will revert to its normal loop bandwidth once lock acquisition has completed.

3.4 Modes of Operation

Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of operation is shown in

Figure 3.1 Modes of Operation on page 5.

The follow-

ing sections describe each of these modes in greater detail.

silabs.com

| Smart. Connected. Energy-friendly.

Rev. 1.1 | 4

Recommended Resources

intercom circuit

Hybrid Power Amplifier 03

TV image intermediate amplifier circuit

FM demodulator

Low Cost Wien Bridge Oscillator

Switched harmonic crystal oscillator

Does anyone know which graphics control is better?: The company wants to build a system that uses graphics controls. It is too troublesome to develop it by ourselves, so we found a few and compared them. Has anyone used the visual graph of Beijing Tuwa...; wisper Embedded System

ARM Study Report (Classic): The very classic ARM learning materials are divided into three parts: ARM image file and execution mechanism, GNU image mechanism, and BIOS source code analysis. The source program is attached to the ...; chych ARM Technology

LPC and STM32, which series do you think is better?: LPC and STM32, which series do you think is better?...; 一条鱼 stm32/stm8

The last post of 2008 - Finalizing MMU and cache (and correcting previous mistakes): In the past two days, I re-read MMU and cache, and got a little understanding of it. Now I put my doubts on the forum again, hoping that everyone can help (I participated in the betting a few days ago...; langniao Embedded System

40 Years of Mobile Base Station History: [align=left][color=rgb(51, 51, 51)][font=-apple-system-font, BlinkMacSystemFont, "][size=17px]Since the birth of mobile communication networks in the late 1970s, mobile base stations have been with ma...; btty038 RF/Wirelessly

【RT-Thread Reading Notes】Network Framework: [size=4][md]For embedded network communication, I rarely come into contact with it. This time I studied the last chapter of this book - Network Framework, and now I summarize it as follows. ## TCP/IP ...; jj1989 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components