CS7054
Low Side PWM FET
Controller
The CS7054 is a monolithic integrated circuit designed primarily to
control the rotor speed of permanent magnet, direct current (DC)
brush motors. It drives the gate of an N channel power MOSFET or
IGBT with a user–adjustable, fixed frequency, variable duty cycle,
pulse width modulated (PWM) signal. The CS7054 can also be used to
control other loads such as incandescent bulbs and solenoids.
Inductive current from the motor or solenoid is recirculated through an
external diode.
The CS7054 accepts a DC level input signal of 0 to 5.0 V to control
the pulse width of the output signal. This signal can be generated by a
potentiometer referenced to the on–chip 5.0 V linear regulator, or a
filtered 0% to 100% PWM signal also referenced to the 5.0 V
regulator.
The IC is placed in a sleep state by pulling the CTL lead below 0.5 V.
In this mode everything on the chip is shut down except for the
on–chip regulator and the overall current draw is less than 275
µA.
There are a number of on–chip diagnostics that look for potential
failure modes and can disable the external power MOSFET.
Features
•
200 mA Peak PWM Gate Drive Output
•
Patented Voltage Compensation Circuit
•
100% Duty Cycle Capability
•
5.0 V,
±
3.0% Linear Regulator
•
Low Current Sleep Mode
•
Overvoltage Protection
•
Overcurrent Protection of External MOSFET/IGBT
•
Output Inhibit
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DIP–14
N SUFFIX
CASE 646
1
SO–16L
DW SUFFIX
CASE 751G
1
14
16
PIN CONNECTIONS AND
MARKING DIAGRAMS
1
OUTPUT
GND
FLT
C
OSC
R
OSC
CTL
NC
DIP–14
1
OUTPUT
GND
FLT
C
OSC
R
OSC
CTL
NC
NC
AWLYYWW
16
V
CC
NC
PGND
INH
I
ADJ
I
SENSE+
I
SENSE–
V
REG
14
V
CC
PGND
INH
I
ADJ
I
SENSE+
I
SENSE–
V
REG
SO–16L
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
CS7054YN14
CS7054YDW16
CS7054YDWR16
Package
DIP–14
SO–16L
Shipping
25 Units/Rail
46 Units/Rail
CS7054
AWLYYWW
CS7054
SO–16L 1000 Tape & Reel
©
Semiconductor Components Industries, LLC, 2001
1
January, 2001 – Rev. 12
Publication Order Number:
CS7054/D
CS7054
MOT+
V
BAT
42.5
µH
R
S
51
1000
µF
1000
µF
OUTPUT
GND
FLT
CS7054
C
OSC
R
OSC
CTL
NC
I
ADJ
I
SENSE+
I
SENSE–
V
REG
V
CC
PGND
INH
10
µF
R
GATE
6
0.01
µF
1.0 M
MOT–
C
FLT
C
OSC
0.25
µF
390 pF
R
CS1
C
CS
51
Ω
0.022
µF
R
CS2
51
Ω
R
SENSE
4.0 mΩ
R
OSC
105 k
PWM
Input
10 k
10 k
P1
100 k
10 k
10
µF
10 k
10 k
10 k
N1
10 k
Figure 1. Application Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Storage Temperature
V
CC
Supply Voltage Range (Load Dump = 26 V w/Series 51
Ω
Resistor) V
CC
Peak Transient Voltage
Input Voltage Range (at any input)
Maximum Junction Temperature
ESD Susceptibility (Human Body Model)
Lead Temperature Soldering
1. 10 seconds max.
2. 60 seconds max above 183°C
*The maximum package power dissipation must be observed.
Wave Solder (through hole styles only) Note 1.
Reflow (SMD styles only) Note 2.
Value
–65 to 150
–0.3 to 30
40
–0.3 to 10
150
2.0
260 peak
230 peak
Unit
°C
V
V
V
°C
kV
°C
°C
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2
CS7054
ELECTRICAL CHARACTERISTICS
(8.0 V < V
CC
< 16 V; –40°C < T
A
< 125°C; unless otherwise specified.)
Characteristic
V
CC
Supply
Operating Current Supply
Quiescent Current
Overvoltage Shutdown
Overvoltage Hysteresis
Control (CTL)
Control Input Current
Sleep Mode Threshold
Sleep Mode Hysteresis
Current Sense
Differential Voltage Sense
I
ADJ
Input Current
Linear Regulator
Output Voltage
Inhibit
Inhibit Threshold
Inhibit Hysteresis
External Drive (OUTPUT)
Output Frequency
Voltage to Duty Cycle Conversion
Output Rise Time
Output Fall Time
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
R
OSC
= 105 kΩ, C
OSC
= 390 pF
V
CC
= 13 V, CTL = 30% V
REG
V
CC
= 13 V, CTL = 70% V
REG
V
CC
= 13 V, R
GATE
= 6.0
Ω,
C
GATE
= 5.0 nF
V
CC
= 13 V, R
GATE
= 6.0
Ω,
C
GATE
= 5.0 nF
V
CC
= 13 V, R
GATE
= 6.0
Ω,
C
GATE
= 5.0 nF
V
CC
= 13 V, R
GATE
= 6.0
Ω,
C
GATE
= 5.0 nF
I
OUT
= 1.0 mA
I
OUT
= –1.0 mA
17
26.3
69.5
–
–
–
–
V
CC
– 1.7
–
20
–
–
0.25
0.3
400
400
–
–
23
38.5
81.5
1.0
1.0
–
–
–
1.3
kHz
%
%
µs
µs
mA
mA
V
V
–
–
40
150
50
325
60
575
% V
REG
mV
V
CC
= 13.2 V
4.85
5.00
5.15
V
I
ADJ
= 51.2% V
REG
and R
CS1
= 51
Ω
I
ADJ
= 0 V to 5.0 V
60.5
–5.0
–
0.3
79.5
2.0
mV
µA
CTL = 0 V to 5.0 V
–
–
–2.0
8.0
50
0.1
10
100
2.0
12
150
µA
% V
REG
mV
V
CC
= 12 V
–
–
–
–
–
18
150
5.0
170
19.5
325
10
275
21
500
mA
µA
V
mV
Test Conditions
Min
Typ
Max
Unit
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3
CS7054
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
DIP–14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO–16L
1
2
3
4
5
6
7, 8, 15
9
10
11
12
13
14
16
PIN SYMBOL
OUTPUT
GND
FLT
C
OSC
R
OSC
CTL
NC
V
REG
I
SENSE–
I
SENSE+
I
ADJ
INH
PGND
V
CC
FUNCTION
MOSFET Gate Drive.
Ground.
Fault time out capacitor.
Oscillator capacitor.
Oscillator resistor.
Pulse width control input.
No connection.
5.0 V linear regulator.
Current sense minus.
Current sense plus.
Current limit adjust.
Output Inhibit.
Power ground for on chip clamp.
Positive power supply input.
GND
V
CC
V
REG
5.0 V Regulator
Overvoltage
Clamp
V
CC
PGND
+
_
CTL
+
_
Reset
Triangle
Oscillator
S
R
Current
Sense
I
SENSE+
Q
+
_
OUTPUT
+
_
INH
I
SENSE–
Timer
Out
In
+
_
I
ADJ
FLT
C
OSC
R
OSC
Figure 2. Block Diagram
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