EP1C3F400 datasheet, PDF - EEWORLD Datasheet

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EP1C3F400: DescriptionFPGA, 20060 CLBS, 405 MHz, PBGA400; Categorysemiconductor Programmable logic devices; File Size544KB，94 Pages; ManufacturerAltera (Intel)

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EP1C3F400 Overview

FPGA, 20060 CLBS, 405 MHz, PBGA400

EP1C3F400 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	400
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	21 X 21 MM, 1.00 MM PITCH, LEAD FREE, FBGA-400
state	ACTIVE
packaging shape	SQUARE
Package Size	GRID ARRAY
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN LEAD
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
organize	20060 CLBS
Maximum FCLK clock frequency	405 MHz
Number of configurable logic modules	20060
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY

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Cyclone

FPGA Family

Data Sheet

March 2003, ver. 1.1

Introduction

Preliminary

Information

The Cyclone

field programmable gate array family is based on a 1.5-V,

0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost-effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

■

Features...

2,910 to 20,060 LEs, see

Table 1

Up to 294,912 RAM bits (36,864 bytes)

Supports configuration through low-cost serial configuration device

Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

Support for 66-MHz, 32-bit PCI standard

Low speed (311 Mbps) LVDS I/O support

Up to two PLLs per device provide clock multiplication and phase

shifting

Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

Support for multiple intellectual property (IP) cores, including

Altera



MegaCore



functions and Altera Megafunctions Partners

Program (AMPP

) megafunctions

Table 1. Cyclone Device Features

Feature

LEs

M4K RAM blocks (128

36 bits)

Total RAM bits

PLLs

Maximum user I/O pins

(1)

Note to

Table 1:

(1)

This parameter includes global clock pins.

EP1C3

2,910

59,904

104

EP1C4

4,000

78,336

301

EP1C6

5,980

92,160

185

EP1C12

12,060

239,616

249

EP1C20

20,060

294,912

301

Altera Corporation

DS-CYCLONE-1.1

Preliminary Information

Cyclone FPGA Family Data Sheet

Table of

Contents

Introduction ........................................................................................................1

Features ............................................................................................................... 1

Table of Contents ...............................................................................................3

Functional Description......................................................................................4

Logic Array Blocks.............................................................................................6

Logic Elements ...................................................................................................9

MultiTrack Interconnect .................................................................................17

Embedded Memory.........................................................................................23

Global Clock Network & Phase-Locked Loops...........................................34

I/O Structure ....................................................................................................44

Power Sequencing & Hot Socketing .............................................................60

IEEE Std. 1149.1 (JTAG) Boundary Scan Support .......................................60

SignalTap II Embedded Logic Analyzer ...................................................... 65

Configuration ...................................................................................................65

Operating Conditions......................................................................................67

Power Consumption........................................................................................73

Timing Model ...................................................................................................73

Software............................................................................................................. 93

Device Pin-Outs ...............................................................................................93

Ordering Information......................................................................................93

Altera Corporation

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